1. MAX® 10 External Memory Interface Overview
2. MAX® 10 External Memory Interface Architecture and Features
3. MAX® 10 External Memory Interface Design Considerations
4. MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for MAX® 10 Devices
6. MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the MAX® 10 External Memory Interface User Guide
2.1. MAX® 10 I/O Banks for External Memory Interface
2.2. MAX® 10 DQ/DQS Groups
2.3. MAX® 10 External Memory Interfaces Maximum Width
2.4. MAX® 10 Memory Controller
2.5. MAX® 10 External Memory Read Datapath
2.6. MAX® 10 External Memory Write Datapath
2.7. MAX® 10 Address/Command Path
2.8. MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. MAX® 10 Low Power Feature
2.12. MAX® 10 Low Power Feature
The MAX® 10 low power feature is automatically activated when the self refresh or low power down modes are activated. The low power feature sends the afi_mem_clk_disable signal to stop the clock used by the controller.
To conserve power, the MAX® 10 UniPHY IP core performs the following functions:
- Tri-states the address and command signals except CKE and RESET_N signals
- Disables the input buffer of DDR input
Note: The MAX® 10 low power feature is available from version 15.0 of the Quartus® Prime software. To enable this feature, regenerate your MAX® 10 UniPHY IP core using the Quartus® Prime software version 15.0 or later.