220.127.116.11. Quartus Prime Project Settings
To set the Intel® Quartus® Prime project setting, add the top level file, Signal Tap file and SDC file to the project, perform the following steps:
- Click Device at Assignments menu, and then click Device and Pin Options in Device dialog box.
- Under Configuration Category, select Active Serial x4 for the Configuration scheme.
- Under Error Detection CRC Category, check the Enable Error Detection CRC_ERROR pin.
- Leave Enable internal scrubbing uncheck.
Note: You can enable Enable internal scrubbing during internal scrubbing feature tryout.
- Set the Divide error check frequency by list to 2.
- Check the Generate SEU sensitivity map file (.smh).
- Click OK to exit Device and Pin Options dialog box.
- Click OK again to exit Device dialog box.
- Click Settings at Assignments menu, select Files category at left panel, add top.v, top.stp and top.sdc to the project.
- Select TimeQuest Timing Analyzer category at left panel, add the top.sdc to SDC files to include in the project.
- Select Signal Tap Logic Analyzer category at left panel, check Enable Signal Tap Logic Analyzer and select the top.stp as the Signal Tap File name.
- Click OK to close the Settings window.
- Click Processing Menu, click Start > Analysis and Synthesis.
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