AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

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ID 683064
Date 10/21/2021
Public
Document Table of Contents

6.2.2.2. Adding Altera IOPLL IP Core

You must instantiate Altera IOPLL IP core in this reference design to generate 3 different clock sources, 10MHz, 20MHz and 100MHz. To add the Altera IOPLL IP core, perform the following steps:

  1. On the IP Catalog Tab, expand Basic Functions, expand Clock; PLLs and Resets, PLL, and then click Altera IOPLL.
  2. Click Add. The Altera IOPLL parameter editor appears.
  3. On PLL tab, at General section, set the Reference Clock Frequency to 50.
  4. Uncheck Enable locked output port.
  5. At Output Clocks section, set Number Of Clocks to 3.
  6. Set the clocks as the following:
    1. For outclk0, set the Clock Name to clk_100and set the Desired Frequency to 100MHz.
    2. For outclk1, set the Clock Name to clk_20 and set the Desired Frequency to 20MHz.
    3. For outclk2, set the Clock Name to clk_10 and set the Desired Frequency to 10MHz.
  7. Click Finish to return to Qsys.
  8. On System Contents tab, an instance of the iopll_0 appears in the system contents table.
  9. Connect the clk port of the clk_0 clock source to the refclk port of the iopll_0.
  10. Connect the clk_reset port of the clk_0 clock source to the reset port of the iopll_0.
  11. Double click the outclk2 of the iopll_0 at Export column to export outclk2 as the clock source for other component outside of this Qsys system. Rename the exported signal as clk_10.
  12. Double click the outclk0 of the iopll_0 at Export column to export outclk0 as the clock source for other component outside of this Qsys system. Rename the exported signal as clk_100.

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