AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

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ID 683064
Date 10/21/2021
Public
Document Table of Contents

4.1.1.1. Enabling the Error Detection CRC_ERROR Pin

To enable the CRC_ERROR pin for external host monitoring purpose, perform the following steps:

  1. On the Assignments menu, click Device.
  2. Click Device and Pin Options and select the Error Detection CRC at the left panel.
  3. Check the Enable Error Detection CRC_ERROR pin.
  4. Select the EDCRC clock divisor from the list of Divide error check frequency by.
    Note: This option provides you with a flexibility to run the EDCRC at a slower speed. However, Intel recommends you to set to the smallest EDCRC clock divisor. Setting a high divisor can impact the error detection time performance. Refer to Arria 10 Handbook SEU Mitigation chapter of the Arria 10 handbook for detection time specification.
  5. Check the Enable open drain on CRC_ERROR pin if you have an external pull up resistor on your board.
  6. Click OK.

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