AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

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ID 683064
Date 10/21/2021
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4.3.2. Correctable and Uncorrectable Error

When an SEU is detected, you can read the EMR data to determine whether the error is correctable or uncorrectable. Intel recommends you to use Altera EMR Unloader IP core in your design. The Altera EMR Unloader IP core interprets the error and reports it at the output.

Table 5.  Correctable and Uncorrectable Error CasesThe table summarizes the correctable and uncorrectable error cases. You do not need to determine whether the current EDCRC operation is in frame-based check-bits or column-based check-bits but you need to know how to interpret the error type of the column-based or frame-based. If the EMR Unloader IP core reports the error type other than 3’b111, the error is correctable and the error will be scrubbed if you turned on internal scrubbing.
Case EDCRC Operation CRC_ERROR Pulse Column-Based Field Frame-Based Field Correctable Remark
A 1 Frame-based check-bits 1 All 0's

Type = 3'b001 or

Type = 3'b010 & bit ≠ 5'h1F or

Type = 3'b011 & bit = 5'h1F

Yes Error will be corrected if internal scrubbing is turned On
B1 Frame-based check-bits 1 All 0's

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h1F

EMR Unloader IP core will set type = 3'b111 if any of above condition met

No The frame-based check-bits will retry for 2 times and enter dead state where CRC_ERROR stays high until FPGA reconfiguration
C Stuck in dead state 1 pulse and stay high after 2nd assertion EMR Unloader IP core set Type = 3'b111 EMR Unloader IP core set type = 3'b111 No CRC_ERROR stays high until FPGA reconfiguration. Refer Case B to understand how EDCRC can stuck in dead state
D Column-based check-bits 1

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h00

EMR Unloader IP core will set type = 3'b111 if any of above condition met

All 0's No Detected uncorrectable error during column-based check-bits
E Column-based check-bits and frame-based check-bits 2

Any type except:

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h00

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h1F

EMR Unloader IP core will set type = 3'b111 if any of above condition met

No Detected uncorrectable error
F Column-based check-bits and frame-based check-bits 2

Any type except:

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h00

Any type except:

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h1F

Yes Error will be corrected if internal scrubbing is turned On
1 Case can occur only when the Frame-based CRC error is detected after the CRAM is configured, such as FPGA configuration, partial PR or CvP. The SEU event is statistically impossible to happen during CRAM configuration, such cases are to cover other problems such as corrupted configuration data or bad CRAM that unable to hold the correct bit setting.

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