AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

Download
ID 683064
Date 10/21/2021
Public
Document Table of Contents

6.2.4.4. Assigning FPGA Pin Location

To assign the clock source pin to your design, perform the following steps:

  1. Launch the Pin Planner from the Assignment menu.
  2. Assign AU33 to inclk input.
  3. Close the Pin Planner.

Did you find the information on this page useful?

Characters remaining:

Feedback Message