6.3. Design Testing with Fault Injection Debugger
The following are the main steps to test your reference design:
- Convert .sof file and .smh file to .jic file.
- Program .jic file to EPCQ-L.
- Launch Signal Tap Logic Analyzer and Fault Inject Debugger.
- Configure the .sof to Arria 10 and reading .smh file with Fault Injection Debugger.
- Start Signal Tap to monitor the signal and injecting an error with Fault Injection Debugger.
- Observe the Signal Tap output.
This section will go through some simple steps to inject faults to the CRAM. For more information about the Fault Injection Debugger, refer to Fault Injection Debugger User Guide.
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