AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

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ID 683064
Date 10/21/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Intel® Quartus® Prime Software SEU FIT Reports 3. Intel® Arria® 10 Error Detection and Correction Feature Architecture 4. Guidelines for Error Detection CRC and Error Correction Feature 5. Guidelines for Embedded Memory ECC Feature 6. Intel® Arria® 10 EDCRC Reference Design 7. Implementing ECC Feature in Intel® Arria® 10 ROM Design 8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 9. Document Revision History for AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices
2. Intel® Quartus® Prime Software SEU FIT Reports x
2.1. Enabling the Projected SEU FIT by Component Usage Report 2.2. SEU FIT Parameters Report 2.3. Projected SEU FIT by Component Usage Report
2.3. Projected SEU FIT by Component Usage Report x
2.3.1. Component FIT Rates 2.3.2. Raw FIT 2.3.3. Utilized FIT 2.3.4. Mitigated FIT 2.3.5. Architectural Vulnerability Factor
2.3.3. Utilized FIT x
2.3.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 2.3.3.2. Considerations for Small Designs
3. Intel® Arria® 10 Error Detection and Correction Feature Architecture x
3.1. Error Detection and Correction for CRAM 3.2. Memory Blocks Error Correction Code Support
3.1. Error Detection and Correction for CRAM x
3.1.1. Error Detection Cyclic Redundancy Check 3.1.2. Recovering from CRC Errors
3.1.1. Error Detection Cyclic Redundancy Check x
3.1.1.1. Column-Based and Frame-Based Check-Bits 3.1.1.2. Error Message Register
4. Guidelines for Error Detection CRC and Error Correction Feature x
4.1. Error Detection 4.2. Enabling Error Correction (Internal Scrubbing) 4.3. Interpreting CRC_ERROR
4.1. Error Detection x
4.1.1. Enabling Error Detection 4.1.2. Reading EMR
4.1.1. Enabling Error Detection x
4.1.1.1. Enabling the Error Detection CRC_ERROR Pin
4.1.2. Reading EMR x
4.1.2.1. Reading EMR using EMR Unloader IP Core 4.1.2.2. Reading EMR using HPS 4.1.2.3. Reading EMR using JTAG Interface
4.3. Interpreting CRC_ERROR x
4.3.1. CRC_ERROR Pin Behavior 4.3.2. Correctable and Uncorrectable Error
6. Intel® Arria® 10 EDCRC Reference Design x
6.1. System Requirements 6.2. Creating Intel® Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys 6.3. Design Testing with Fault Injection Debugger
6.2. Creating Intel® Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys x
6.2.1. Starting Intel® Quartus® Prime Software and Opening the Reference Design Project 6.2.2. Creating New Qsys System 6.2.3. Generating Qsys System 6.2.4. Integrating Qsys System into Quartus Prime Project
6.2.2. Creating New Qsys System x
6.2.2.1. Specifying Target FPGA and Clock Settings 6.2.2.2. Adding Altera IOPLL IP Core 6.2.2.3. Adding EMR Unloader IP Core 6.2.2.4. Adding Advance SEU Detection IP Core 6.2.2.5. Adding Fault Injection IP Core 6.2.2.6. Adding Avalon-ST Splitter 6.2.2.7. Adding Serial Flash Controller
6.2.4. Integrating Qsys System into Quartus Prime Project x
6.2.4.1. Generating In-System Source and Probe IP Core 6.2.4.2. Quartus Prime Project Settings 6.2.4.3. Assigning ASD Regions 6.2.4.4. Assigning FPGA Pin Location 6.2.4.5. Compiling the Project
6.3. Design Testing with Fault Injection Debugger x
6.3.1. Converting .sof File and .smh File to .jic File 6.3.2. Programing .jic File into EPCQ-L 6.3.3. Launching Signal Tap Logic Analyzer 6.3.4. Configuring Intel® Arria® 10 and Reading .smh File with Fault Injection Debugger 6.3.5. Injecting Error with Fault Injection Debugger
7. Implementing ECC Feature in Intel® Arria® 10 ROM Design x
7.1. Examples of Error Detection and Correction
1. Overview
2. Intel® Quartus® Prime Software SEU FIT Reports
3. Intel® Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Intel® Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Intel® Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

9. Document Revision History for AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

Document Version Changes
2021.10.21 Added section about the Intel® Quartus® Prime software SEU FIT reports.
2020.04.13
  • Updated the Implementing ECC Feature in Intel® Arria® 10 ROM Design chapter to show steps to implement ECC feature using the RAM: 2-PORT Intel FPGA IP.
  • Remove the Arria 10 ROM with ECC Reference Design Files link.
2019.08.09 Added steps to modify .jam file for use in a multi-device JTAG chain.
2018.09.04
  • Added a note in System Requirements stating that a licensed version of Intel® Quartus® Prime software is required to generate SMH files.
  • Updated hyperlinks.
Date Version Changes
March 2017 2017.03.15 Rebranded as Intel.
February 2017 2017.02.13
  • Updated Timing Diagram for Column-Based Check-Bits diagram description.
  • Added note to Case A and B in Correctable and Uncorrectable Error Cases table.
  • Updated device development kit ordering part number.
  • Added note to Creating Intel® Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys to state the availability of a10-seu-complete.zip design and skipping pregenerated steps.
  • Updated device selection in Converting .sof File and .smh File to .jic File.
October 2016 2016.10.31
  • Added ROM with ECC Reference Design.
  • Updated EDCRC reference design target device and reference design file.
March 2016 2016.03.03 Updated CRC_ERROR pin behavior when uncorrectable error cannot be located.
March 2016 2016.03.02 Initial release.
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