AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

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ID 683064
Date 10/21/2021
Public
Document Table of Contents

9. Document Revision History for AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

Document Version Changes
2021.10.21 Added section about the Intel® Quartus® Prime software SEU FIT reports.
2020.04.13
  • Updated the Implementing ECC Feature in Intel® Arria® 10 ROM Design chapter to show steps to implement ECC feature using the RAM: 2-PORT Intel FPGA IP.
  • Remove the Arria 10 ROM with ECC Reference Design Files link.
2019.08.09 Added steps to modify .jam file for use in a multi-device JTAG chain.
2018.09.04
  • Added a note in System Requirements stating that a licensed version of Intel® Quartus® Prime software is required to generate SMH files.
  • Updated hyperlinks.
Date Version Changes
March 2017 2017.03.15 Rebranded as Intel.
February 2017 2017.02.13
  • Updated Timing Diagram for Column-Based Check-Bits diagram description.
  • Added note to Case A and B in Correctable and Uncorrectable Error Cases table.
  • Updated device development kit ordering part number.
  • Added note to Creating Intel® Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys to state the availability of a10-seu-complete.zip design and skipping pregenerated steps.
  • Updated device selection in Converting .sof File and .smh File to .jic File.
October 2016 2016.10.31
  • Added ROM with ECC Reference Design.
  • Updated EDCRC reference design target device and reference design file.
March 2016 2016.03.03 Updated CRC_ERROR pin behavior when uncorrectable error cannot be located.
March 2016 2016.03.02 Initial release.

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