AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

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ID 683064
Date 10/21/2021
Public
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4.1.2.2. Reading EMR using HPS

The FPGA Manager in the HPS has the ability to monitor the CRC_ERROR status pin and to retrieve the error symptom, location and type. You can choose to enable the CRC error interrupt from the FPGA Manager, followed by CRC error information extraction from respective registers.

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