AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

ID 683064
Date 10/21/2021
Document Table of Contents

6.2.4. Integrating Qsys System into Quartus Prime Project

To complete the reference design, you must perform the following tasks:

  • Generate In-System Source and Probe (ISSP) IP core
  • Intel® Quartus® Prime project setting and add the following files (provided in download package) to the project:
    • Top.v—instantiate the Qsys system module and connect all other IP cores
    • Top.stp—monitor some key signals with Signal Tap tool
    • Top.sdc—timing constraint
  • Assign ASD regions to up counter and down counter
  • Assign FPGA device and pin locations
  • Compile the project