AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

ID 683064
Date 10/21/2021
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7.1. Examples of Error Detection and Correction

The following examples initiate the ROM content using the .mif file with the associated address shown in the following table.
Table 6.  Example of ROM Content Initialization
Address ROM content
00h 32h
01h 33h
02h 34h

:

:

:

:

1Dh 4Fh
1Eh 50h
1Fh 51h

Single-bit Error

The following figure shows an example of a single-bit error waveform following an SEU event impact on ROM content of address 1Fh. The waveform indicates that there is a two-clock cycle latency on the output with respect to the associated read address. When the ROM content is free from bit-flip, the eccstatus signal shows 2b’00. The ROM content of address 1Fh was initialized with data 51h using the .mif file as shown in the Example of ROM Content Initialization table. The ECC status signal shows 2b’10 indicating a single error bit is detected at the ROM content of address 1Fh. The IP corrects the error at the output.

Figure 14. Single Bit Error Waveform

Three Adjacent Bits Error

The following figure shows an example of three adjacent bits error waveform following a multi-bit upset (MBU) event on the ROM content of address 1Fh. The waveform indicates that there is a two-clock cycle latency on the output with respect to the associated read address. The ROM content of address 1Fh was initialized with data 51h using the .mif file as shown in the Example of ROM Content Initialization table. The ECC status signal shows 2b’11 which indicates 3 adjacent bits error detected at the ROM content of the address 1Fh and uncorrectable data appears at the output.

Figure 15. 3 Adjacent Bits Error Waveform