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1. Overview
2. Intel® Quartus® Prime Software SEU FIT Reports
3. Intel® Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Intel® Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Intel® Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices
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4.1.1. Enabling Error Detection
There are two methods to turn on Intel® Arria® 10 error detection CRC feature based on your application needs.
- If your design detects and reads the EMR using user logic, you need to instantiate the EMR Unloader IP core which will automatically turn the EDCRC feature on.
- If you want to monitor SEU with the external host and do not need to read the EMR from user logic, you can turn on EDCRC feature by enabling CRC_ERROR pin in your Intel® Quartus® Prime project.
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