AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

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ID 683064
Date 10/21/2021
Public
Document Table of Contents

6.2.2.4. Adding Advance SEU Detection IP Core

You must instantiate the ASD IP core for sensitivity processing and to validate the hierarchy tagging feature. To add ASD IP core, perform the following steps:

  1. On the IP Catalog tab, expand Basic Functions, expand Configuration and Programming, and then click Altera Advanced SEU Detection.
  2. Click Add. The Altera Advanced SEU Detection parameter editor appears.
  3. Leave the CRC error cache depth list default selection at 8.
  4. Set Largest ASD region ID used to 3.
  5. Check the Use on-chip sensitivity processing.
  6. Set Memory interface address width to 32.
  7. Set Sensitivity Data start address to 0x02000000.
  8. Click Finish to return to Qsys. On System Contents tab, an instance of the adv_seu_detection_0 appears in the system contents table.
  9. Connect the clk_reset port of the clk_0 clock source to the reset port of the adv_seu_detection_0.
  10. Double click the cache_comparison_off, and errors port of adv_seu_detection_0 at Export column to export them for external access, leave the name default.

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