AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

ID 683064
Date 10/21/2021
Document Table of Contents Specifying Target FPGA and Clock Settings

To specify target FPGA and clock settings in Qsys, perform the following steps:

  1. Click Device Family in View menu, select the Device Family that matches the Intel® Arria® 10 device you are targeting. Warning will appear if the selected device family does not match Intel® Quartus® Prime project settings, you need to make sure your selected device in Intel® Quartus® Prime project settings match to your selected Device Family in Qsys.
  2. On the System Contents tab, double click the clk_0 component. In the Parameters tab for clk_0, set the Clock frequency to 50MHz.
    Next, you begin to add other IP cores to the Qsys system.