AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

ID 683064
Date 10/21/2021
Document Table of Contents
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5. Guidelines for Embedded Memory ECC Feature

The Intel® Arria® 10 FIFO Intel® FPGA IP supports embedded memory ECC for M20K memory blocks. The built-in ECC feature in the Intel® Arria® 10 devices can perform:

  • Single-error detection and correction
  • Double-adjacent-error detection and correction
  • Triple-adjacent-error detection

You can turn on FIFO Embedded ECC feature by enabling enable_ecc parameter in the FIFO Intel® FPGA IP parameter editor.

Note: Embedded memory ECC feature is only available for M20K memory block type.
Note: The embedded memory ECC supports variable data width. When ECC is enabled, RAM combines multiple M20K blocks in the configuration of 32 (width) x 512 (depth) to fulfill your instantiation. The unused data width will be tied to the VCC internally.
Note: The embedded memory ECC feature is not supported in mixed-width mode.
Figure 10. ECC Option in FIFO Intel® FPGA IP Parameter Editor

When you enable the ECC feature, a 2-bit wide error correction status port (eccstatus[1:0]) will be created in the generated FIFO entity. These status bits indicate whether the data that is read from the memory has an error in single-bit with correction, fatal error with no correction, or no error bit.

  • 00: No error
  • 01: Illegal
  • 10: A correctable error occurred and the error has been corrected at the outputs; however, the memory array has not been updated.
  • 11: An uncorrectable error occurred and uncorrectable data appears at the output