AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

ID 683064
Date 10/21/2021
Document Table of Contents

7. Implementing ECC Feature in Intel® Arria® 10 ROM Design

The ROM IP core does not have ECC selection in the user interface. However, you can enable the ECC feature for ROM design by using the RAM: 2-PORT IP core.
Steps to implement the ECC feature in Intel® Arria® 10 ROM Design.
  1. Instantiate the RAM: 2-PORT IP with the following settings:

Parameters Settings
Operation Mode Select With one read port and one write port.
Use different data width on different ports Disable
RAM Block Type Select M20K.
Create byte enable for port A and Create byte enable for port A Disable
Enable Error Correction Checking Enable
Do you want to specify the initial content of the memory? Select Yes, use this file for the memory content data and specify the location of the file.

  1. Connect the signals of the IP according to the following figure.
    Figure 13. ROM with ECC Feature Using RAM: 2-PORT IP