6.2. Creating Intel® Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys
The a10-seu.zip reference design consists of:
- a10_seu.qar—the project archive file
- top.v—the top level module of the project
- top.sdc—the timing constraint file
- top.stp—the Signal Tap file
In this design, you will use Platform Designer (Standard) to connect the Intel SEU-related IP cores together. IP core to be connected are EMR Unloader IP core, Fault Injection IP core and Advanced SEU Detection IP core. Some other IP cores are also needed to make the design complete, which are Altera IOPLL IP core, AVST Splitter and Serial Flash Controller IP core.
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