AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

ID 683064
Date 10/21/2021
Document Table of Contents

6.2. Creating Intel® Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys

The reference design consists of:

  • a10_seu.qar—the project archive file
  • top.v—the top level module of the project
  • top.sdc—the timing constraint file
  • top.stp—the Signal Tap file
Note: The consists of a fully compiled and output files-ready reference design. You can refer directly to Design Testing with Fault Injection Debugger if you choose to use this complete design as a reference.

In this design, you will use Platform Designer (Standard) to connect the Intel SEU-related IP cores together. IP core to be connected are EMR Unloader IP core, Fault Injection IP core and Advanced SEU Detection IP core. Some other IP cores are also needed to make the design complete, which are Altera IOPLL IP core, AVST Splitter and Serial Flash Controller IP core.

Figure 11. Arria 10 SEU Fault Injection and Hierarchy Tagging Design