Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents Zero-Delay Buffer Mode

In zero-delay buffer (ZDB) mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through the device. When using this mode, use the same I/O standard for the input clock and output clocks to ensure clock alignment at the input and output pins. PLL_CLKOUTn pin is not supported for single-ended I/O standard in this mode.

Figure 15. Example of Phase Relationship Between the PLL Clocks in ZDB Mode