Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents

1.3. PLLs Overview

Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking.

You can use the PLLs as follows:

  • Zero-delay buffer
  • Jitter attenuator
  • Low-skew fan-out buffer
  • Frequency synthesizer
  • Reduce the number of oscillators required on the board
  • Reduce the clock pins used in the device by synthesizing multiple clock frequencies from a single reference clock source
  • On-chip clock de-skew
  • Dynamic phase shift
  • Counters reconfiguration
  • Bandwidth reconfiguration
  • Programmable output duty cycle
  • PLL cascading
  • Reference clock switchover
  • Drive the analog-to-digital converter (ADC) clock