Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents Manual Clock Switchover

In manual clock switchover mode, the clkswitch signal controls whether inclk0 or inclk1 is selected as the input clock to the PLL. By default, inclk0 is selected.

A clock switchover event is initiated when the clkswitch signal transitions from logic low to logic high, and is being held high for at least three inclk cycles. You must bring the clkswitch signal back to low again to perform another switchover event. If you do not require another switchover event, you can leave the clkswitch signal in a logic high state after the initial switch. Pulsing the clkswitch signal high for at least three inclk cycles performs another switchover event.

If inclk0 and inclk1 have different frequencies and are always running, the minimum amount of time for which clkswitch signal is high must be greater than or equal to three of the slower-frequency inclk0 and inclk1 cycles.