Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents

6.1.3. Programmable Bandwidth Parameter Settings

You can configure the bandwidth of the Avalon ALTPLL Intel® FPGA IP on the Bandwidth/SS page of the Avalon ALTPLL Intel® FPGA IP parameter editor.

Table 17.  Bandwidth Configuration Parameter Editor Settings
Parameter Value Description

The Avalon ALTPLL Intel® FPGA IP parameter editor chooses the best possible bandwidth values to achieve the desired PLL settings. In some cases, you can get a bandwidth value outside the Low and High preset range.

You can use the programmable bandwidth feature with the clock switchover feature to get the PLL output settings that you desire. You must set the bandwidth to Auto if you want to enable the spread-spectrum feature.

Preset Low PLL with a low bandwidth has better jitter rejection but a slower lock time.
Medium PLL with a medium bandwidth has a balance between lock time and jitter rejection.
High PLL with a high bandwidth has a faster lock time but tracks more jitter.

The table on the right in the Bandwidth/SS page shows the values of the following components:

  • Charge pump current
  • Loop filter resistance
  • Loop filter capacitance
  • M counter

These parameter settings create no additional top-level ports.