Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents

6.1.7. Output Clocks Parameter Settings

The Output Clocks page of the Avalon ALTPLL Intel® FPGA IP parameter editor contains the parameter settings of the clock output signals. You can configure the c0, c1, c2, c3, and c4 clock output signals of the Avalon ALTPLL Intel® FPGA IP.

Each option has the following two columns:

  • Requested settings—The settings that you want to implement.
  • Actual settings—The settings closest values that can be implemented in the PLL circuit to best approximate the requested settings.

Use the values in the actual settings column as a guide to adjust the requested settings. If the requested settings for one of the output clocks cannot be approximated, the Avalon ALTPLL Intel® FPGA IP parameter editor produces a warning message at the top of every page.

Table 21.  Output Clocks Parameter Editor Settings
Parameter Value Description
Use this clock On or Off

Turn on this option to generate an output clock port in your Avalon ALTPLL instance.

The output clock port that is to be compensated for is enabled by default. It cannot be disabled, unless you select a different output clock port to be compensated for.

Enter output clock frequency Specify the frequency of the output clock signal.
Enter output clock parameters Specify the output clock parameters instead of the frequency.
Clock multiplication factor Specify the clock multiplication factor of the signal.
Clock division factor Specify the clock division factor of the signal.
Clock phase shift

Set the programmable phase shift for an output clock signals.

The smallest phase shift is 1/8 of VCO period. For degree increments, the maximum step size is 45 degrees. You can set smaller steps using the Clock multiplication factor and Clock division factor options.

For example, if the post-scale counter is 32, the smallest phase shift step is 0.1°. The up and down buttons let you cycle through phase shift values. Alternatively, you can enter a number in the phase shift field manually instead of using the buttons.

Clock duty cycle (%) Set the duty cycle of the output clock signal.
Per Clock Feasibility Indicators

Indicate output clocks that contain unachievable settings.

The output clock name in red is the name of the clock with unachievable settings. The clock listed in green has no settings issues, and the grayed-out names are the unselected output clocks. You must adjust the requested settings for the affected output clocks to resolve the warning messages.

The Avalon ALTPLL Intel® FPGA IP parameter editor calculates the simplest fraction, and displays it in the actual settings column. You can use the copy button to copy values from the actual settings to the requested settings.

Figure 30. PLL Output Clock Frequency

For example, if the input clock frequency is 100 MHz, and the requested multiplication and division factors are 205 and 1025 respectively, the output clock frequency is calculated as 100 × 205/1025=20 MHz. The actual settings reflect the simplest fraction—the actual multiplication factor is 1, and the actual division factor is 5.