Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents Normal Mode

In normal mode, the PLL fully compensates the delay introduced by the GCLK network. An internal clock in normal mode is phase-aligned to the input clock pin. In this mode, the external clock output pin has a phase delay relative to the input clock pin. The Intel® Quartus® Prime software Timing Analyzer reports any phase difference between the two.

Figure 14. Example of Phase Relationship Between the PLL Clocks in Normal Compensation Mode