3.3.4. Guideline: Output Clocks
Each Intel® MAX® 10 PLL supports up to five output clocks. You can use the output clock port as a core output clock or an external output clock port. The core output clock feeds the FPGA core and the external output clock feeds the dedicated pins on the FPGA.
The Avalon ALTPLL Intel® FPGA IP does not have a dedicated output enable port. You can disable the PLL output using the areset signal to disable the PLL output counters.