Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
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4.2.1. Expanding the PLL Lock Range

The PLL lock range is between the minimum (PLL Freq Min Lock parameter) and maximum (PLL Freq Max Lock parameter) input frequency values for which the PLL can achieve lock. Changing the input frequency might cause the PLL to lose lock, but if the input clock remains within the minimum and maximum frequency specifications, the PLL is able to achieve lock. The Intel® Quartus® Prime software shows these input frequency values in the PLL Summary report located under the Resource Section of the Fitter folder in the Compilation Report.

The Intel® Quartus® Prime software does not necessarily pick values for the PLL parameters to maximize the lock range. For example, when you specify a 75 MHz input clock in the Avalon ALTPLL Intel® FPGA IP parameter editor, the actual PLL lock range might be between 70 MHz to 90 MHz. If your application requires a lock range of 50 MHz to 100 MHz, the default lock range of this PLL is insufficient.

For devices that support clock switchover in PLLs, you can use the Avalon ALTPLL Intel® FPGA IP parameter editor to maximize the lock range.

To extract valid parameter values to maximize your PLL lock range, perform the following steps:

  1. In the schematic editor, double-click the Avalon ALTPLL instance in your design to open the Avalon ALTPLL parameter editor.
  2. On the General/Modes page, for What is the frequency of the inclk0 input?, type the value of the low end of your desired PLL lock range.
    For example, if your application requires a lock range of 50 MHz to 100 MHz, type 50 MHz.
  3. On the Inputs/Lock page, turn on Create output file(s) using the 'Advanced' PLL parameters.
  4. On the Clock switchover page, turn on Create an 'inclk1' input for a second input clock and enter the high end of your lock range as the frequency for inclk1.
    For example, if your application requires a lock range of 50 MHz to 100 MHz, type 100 MHz.
  5. Set the rest of the parameters in the remaining pages of the Avalon ALTPLL Intel® FPGA IP parameter editor.
  6. Compile your project and note the lock range shown in the PLL Usage Summary report. If it is satisfactory, note all of the values for the PLL from this report, such as the M value, N value, charge pump current, loop filter resistance, and loop filter capacitance.
  7. In the schematic editor, double-click the Avalon ALTPLL instance in your design to open the Avalon ALTPLL parameter editor.
  8. On the Clock switchover page, turn off Create an 'inclk1' input for a second input clock.
  9. Click Finish to update the PLL wrapper file.
  10. In a text editor, open the PLL wrapper file. Modify all of the values for the parameters listed in step 6. Save the changes.
    • If the wrapper file is in Verilog format, go to the defparam section.
    • If the wrapper file is in VHDL HDL, go to the Generic Map section.
  11. Compile your project.
  12. Check the PLL Summary report to confirm that the PLL lock range meets your requirements. The modified PLL should have the desired lock range.

If your input clock frequency is too close to the end of the desired PLL lock range—for example the low end of the desired lock range is 50 MHz and the input clock frequency is 50 MHz, the PLL might not maintain lock when the input clock has jitter or the frequency drifts below 50 MHz. You may choose to expand your PLL lock range to ensure your expected input clock frequency is further from the end of the range. For this example, you can enter 45 MHz and 105 MHz to ensure that your target lock range of 50 MHz to 100 MHz is within the PLL lock range.

The Intel® Quartus® Prime software prompts an error message if it is unable to implement your preferred lock range using this procedure. Therefore, you have to look into other options, such as PLL reconfiguration, to support your input frequency range.