Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
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2.1.5. Global Clock Control Block

The clock control block drives GCLKs. The clock control blocks are located on each side of the device, close to the dedicated clock input pins. GCLKs are optimized for minimum clock skew and delay.

The clock control block has the following functions:

  • Dynamic GCLK clock source selection (not applicable for DPCLK pins and internal logic input)
  • GCLK multiplexing
  • GCLK network power down (dynamic enable and disable)
Table 3.  Clock Control Block Inputs
Input Description
Dedicated clock input pins Dedicated clock input pins can drive clocks or global signals, such as synchronous and asynchronous clears, presets, or clock enables onto given GCLKs.
DPCLK pins DPCLK pins are bidirectional dual function pins that are used for high fan-out control signals, such as protocol signals, TRDY and IRDY signals for PCI via the GCLK. Clock control blocks that have inputs driven by DPCLK pins cannot drive PLL inputs.
PLL counter outputs PLL counter outputs can drive the GCLK.
Internal logic You can drive the GCLK through logic array routing to enable the internal logic elements (LEs) to drive a high fan-out, low-skew signal path. Clock control blocks that have inputs driven by internal logic cannot drive PLL inputs.
Figure 3. Clock Control Block

Each Intel® MAX® 10 device has a maximum of 20 clock control blocks. There are five clock control blocks on each side of the device.

Each PLL generates five clock outputs through the c[4..0] counters. Two of these clocks can drive the GCLK through a clock control block.

From the Clock Control Block Inputs table, only the following inputs can drive into any given clock control block:

  • Two dedicated clock input pins
  • Two PLL counter outputs
  • One DPCLK pin
  • One source from internal logic

The output from the clock control block in turn feeds the corresponding GCLK. The GCLK can drive the PLL input if the clock control block inputs are outputs of another PLL or dedicated clock input pins. Normal I/O pins cannot drive the PLL input clock port.

Figure 4. Clock Control Block on Each Side of the Device

Out of these five inputs to any clock control block, the two clock input pins and two PLL outputs are dynamically selected to feed a GCLK. The clock control block supports static selection of the signal from internal logic.