Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents Source Synchronous Mode

If the data and clock arrive at the same time at the input pins, the phase relationship between the data and clock remains the same at the data and clock ports of any I/O element input register.

You can use this mode for source synchronous data transfers. Data and clock signals at the I/O element experience similar buffer delays as long as both signals use the same I/O standard.

Figure 12. Example of Phase Relationship Between Clock and Data in Source Synchronous Mode

Source synchronous mode compensates for clock network delay, including any difference in delay between the following two paths:

  • Data pin to I/O element register input
  • Clock input pin to the PLL PFD input

For all data pins clocked by a source synchronous mode PLL, set the input pin to the register delay chain in the I/O element to zero in the Intel® Quartus® Prime software. All data pins must use the PLL COMPENSATED logic option in the Intel® Quartus® Prime software.