Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents

2.3.6. PLL Control Signals

You can use the following three signals to observe and control the PLL operation and resynchronization.


Use the pfdena signal to maintain the last locked frequency so that your system has time to store its current settings before shutting down.

The pfdena signal controls the PFD output with a programmable gate. The PFD circuit is enabled by default. When the PFD circuit is disabled, the PLL output does not depend on the input clock, and tends to drift outside of the lock window.


The areset signal is the reset or resynchronization input for each PLL. The device input pins or internal logic can drive these input signals.

When you assert the areset signal, the PLL counters reset, clearing the PLL output and placing the PLL out of lock. The VCO is then set back to its nominal setting. When the areset signal is deasserted, the PLL resynchronizes to its input as it relocks.

The assertion of the areset signal does not disable the VCO, but instead resets the VCO to its nominal value. The only time that the VCO is completely disabled is when you do not have a PLL instantiated in your design.


The locked output indicates that the PLL has locked onto the reference clock and the PLL clock outputs are operating at the desired phase and frequency set in the Avalon ALTPLL Intel® FPGA IP parameter editor.

Intel recommends using the areset and locked signals in your designs to control and observe the status of your PLL. This implementation is illustrated in the following figure.

Figure 11. locked Signal Implementation
Note: If you use the Signal Tap logic analyzer tool to probe the locked signal before the D flip-flop, the locked signal goes low only when areset is deasserted. If the areset signal is not enabled, the extra logic is not implemented in the Avalon ALTPLL Intel® FPGA IP.