Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Public
Document Table of Contents
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3.1.2. Guideline: Connectivity Restrictions

The following guidelines describe the restrictions associated with the signal sources that can drive the inclk input:

  • You must use the inclk ports that are consistent with the clkselect ports.
  • When you are using multiple input sources, the inclk ports can only be driven by the dedicated clock input pins and the PLL clock outputs.
  • If the clock control block feeds any inclk port of another clock control block, both clock control blocks must be able to be reduced to a single clock control block of equivalent functionality.
  • When you are using the glitch-free switchover feature, the clock you are switching from must be active. If the clock is not active, the switchover circuit cannot transition from the clock you originally selected.