Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents
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2.1.7. Clock Enable Signals

The Intel® MAX® 10 devices support clkena signals at the GCLK network level. This allows you to gate off the clock even when a PLL is used. After reenabling the output clock, the PLL does not need a resynchronization or relock period because the circuit gates off the clock at the clock network level. In addition, the PLL can remain locked independent of the clkena signals because the loop-related counters are not affected.

Figure 5. clkena Implementation
Note: The clkena circuitry controlling the C0 output of the PLL to an output pin is implemented with two registers instead of a single register.
Figure 6. Example Waveform of clkena Implementation with Output EnableThe clkena signal is sampled on the falling edge of the clock (clkin). This feature is useful for applications that require low power or sleep mode.

The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during PLL resynchronization.