2.1.7. Clock Enable Signals
The Intel® MAX® 10 devices support clkena signals at the GCLK network level. This allows you to gate off the clock even when a PLL is used. After reenabling the output clock, the PLL does not need a resynchronization or relock period because the circuit gates off the clock at the clock network level. In addition, the PLL can remain locked independent of the clkena signals because the loop-related counters are not affected.
The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during PLL resynchronization.