Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents

2.3.1. PLL Architecture

The main purpose of a PLL is to synchronize the phase and frequency of the voltage-controlled oscillator (VCO) to an input reference clock.

Figure 7.  Intel® MAX® 10 PLL High-Level Block DiagramEach clock source can come from any of the two or four clock pins located on the same side of the device as the PLL.

Phase-Frequency Detector (PFD)

The PFD has inputs from the feedback clock, fFB, and the input reference clock, fREF. The PLL compares the rising edge of the input reference clock to a feedback clock using a PFD. The PFD produces an up or down signal that determines whether the VCO needs to operate at a higher or lower frequency.

Charge Pump (CP)

If the charge pump receives a logic high on the up signal, current is driven into the loop filter. If the charge pump receives a logic high on the down signal, current is drawn from the loop filter.

Loop Filter (LF)

The loop filter converts the up and down signals from the PFD to a voltage that is used to bias the VCO. The loop filter filters out glitches from the charge pump and prevents voltage overshoot, which minimizes jitter on the VCO.

Voltage-Controlled Oscillator (VCO)

The voltage from the charge pump determines how fast the VCO operates. The VCO is implemented as a four-stage differential ring oscillator. A divide counter, M, is inserted in the feedback loop to increase the VCO frequency, fVCO, above the input reference frequency, fREF.

The VCO frequency is determined using the following equation:

fVCO = fREF × M = fIN × M/N ,

where fIN is the input clock frequency to the PLL and N is the pre-scale counter.

The VCO frequency is a critical parameter that must be between 600 and 1,300 MHz to ensure proper operation of the PLL. The Intel® Quartus® Prime software automatically sets the VCO frequency within the recommended range based on the clock output and phase shift requirements in your design.

Post-Scale Counters (C)

The VCO output can feed up to five post-scale counters (C0, C1, C2, C3, and C4). These post-scale counters allow the PLL to produce a number of harmonically-related frequencies.

Internal Delay Elements

The Intel® MAX® 10 PLLs have internal delay elements to compensate for routing on the GCLK networks and I/O buffers. These internal delays are fixed.

PLL Outputs

The Intel® MAX® 10 PLL supports up to 5 GCLK outputs and 1 dedicated external clock output. The output frequency, fOUT, to the GCLK network or dedicated external clock output is determined using the following equation:

fREF = fIN/N and

fOUT = fVCO/C = (fREF × M)/C = (fIN × M)/(N × C),

where C is the setting on the C0, C1, C2, C3, or C4 counter.