Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents

3.3.1. Guideline: PLL Control Signals

You must include the areset signal in your designs if one of the following conditions is true:

  • PLL reconfiguration or clock switchover is enabled in your design.
  • Phase relationships between the PLL input clock and output clocks must be maintained after a loss-of-lock condition.
  • The input clock to the PLL is toggling or unstable at power-up.
  • The areset signal is asserted after the input clock is stable and within specifications.