Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents

6.1.1. Operation Modes Parameter Settings

You can set the operation mode for PLL in the General/Modes page of the Avalon ALTPLL Intel® FPGA IP parameter editor.

Table 16.  Operation Mode Parameter Editor Settings
Parameter Value Description
Which device speed grade will you be using? Any, 7, or 8 Specify the speed grade if you are not already using a device with the fastest speed. The lower the number, the faster the speed grade.
What is the frequency of the inclock0 input? Specify the frequency of the input clock signal.
Use the feedback path inside the PLL In normal mode, In source-synchronous compensation mode, In zero-delay buffer mode, or With no compensation

Specify which operation mode to use.

For source-synchronous mode and zero-delay buffer mode, you must make PLL Compensation assignments using the Assignment Editor in addition to setting the appropriate mode in the IP. The assignment allows you to specify an output pin as a compensation target for a PLL in zero-delay buffer mode, or to specify an input pin or group of input pins as compensation targets for a PLL in source-synchronous mode.

Which output clock will be compensated for? C0, C1, C2, C3, or C4

Specify which PLL output port to compensate.

The drop down list contains all output clock ports for the selected device. The correct output clock selection depends on the operation mode that you select.

For example, for normal mode, select the core output clock. For zero-delay buffer mode, select the external output clock.