Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents

2.3.8. PLL External Clock Output

Each PLL in the Intel® MAX® 10 devices supports one single-ended clock output or one differential clock output. Only the C0 output counter can feed the dedicated external clock outputs without going through the GCLK. C0 and all other output counters can feed other I/O pins through the GCLK.

Figure 16. PLL External Clock Output

Each pin of a differential output pair is 180° out of phase. To implement the 180° out-of-phase pin in a pin pair, the Intel® Quartus® Prime software places a NOT gate in the design into the I/O element.

The clock output pin pairs support the following I/O standards:

  • Same I/O standard as the standard output pins (in the top and bottom banks)
  • LVDS
  • Differential high-speed transceiver logic (HSTL)
  • Differential SSTL

The Intel® MAX® 10 PLLs can drive out to any regular I/O pin through the GCLK. You can also use the external clock output pins as general-purpose I/O pins if you do not require any external PLL clocking.