Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents Counter-to-Counter Cascading

The Intel® MAX® 10 PLLs support post-scale counter cascading to create counters larger than 512. This is implemented by feeding the output of one C counter into the input of the next C counter.
Figure 23. Counter-to-Counter Cascading

When cascading counters to implement a larger division of the high-frequency VCO clock, the cascaded counters behave as one counter with the product of the individual counter settings.

For example, if C0 = 4 and C1 = 2, the cascaded value is C0 x C1 = 8.

The Intel® Quartus® Prime software automatically sets all the post-scale counter values for cascading in the configuration file. Post-scale counter cascading cannot be performed using PLL reconfiguration.