2.3.12. Clock Switchover
The clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature for clock redundancy or for a dual-clock domain application where a system turns on the redundant clock if the previous clock stops running. The design can perform clock switchover automatically when the clock is no longer toggling or based on a user-controlled signal, clkswitch.
The following clock switchover modes are supported in Intel® MAX® 10 PLLs:
- Automatic switchover—The clock sense circuit monitors the current reference clock. If the current reference clock stops toggling, the reference clock automatically switches to inclk0 or inclk1 clock.
- Manual clock switchover—The clkswitch signal controls the clock switchover. When the clkswitch signal goes from logic low to high, and stays high for at least three clock cycles, the reference clock to the PLL switches from inclk0 to inclk1, or vice-versa.
- Automatic switchover with manual override—This mode combines automatic switchover and manual clock switchover. When the clkswitch signal goes high, it overrides the automatic clock switchover function. As long as the clkswitch signal is high, any further switchover action is blocked.