Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents

2.3.5. PLL Counter to GCLK Connections

Table 6.   Intel® MAX® 10 PLL Counter Connectivity to the GCLK Networks
PLL Counter Output GCLK
PLL1_C0 GCLK[0,3,15,18]
PLL1_C1 GCLK[1,4,16,19]
PLL1_C2 GCLK[0,2,15,17]
PLL1_C3 GCLK[1,3,16,18]
PLL1_C4 GCLK[2,4,17,19]
PLL2_C0 GCLK[5,8,10,13]
PLL2_C1 GCLK[6,9,11,14]
PLL2_C2 GCLK[5,7,10,12]
PLL2_C3 GCLK[6,8,11,13]
PLL2_C4 GCLK[7,9,12,14]
PLL3_C0 5 GCLK[0,3,10,13]
PLL3_C1 5 GCLK[1,4,11,14]
PLL3_C2 5 GCLK[0,2,10,12]
PLL3_C3 5 GCLK[1,3,11,13]
PLL3_C4 5 GCLK[2,4,12,14]
PLL4_C0 5 GCLK[5,8,15,18]
PLL4_C1 5 GCLK[6,9,16,19]
PLL4_C2 5 GCLK[5,7,15,17]
PLL4_C3 5 GCLK[6,8,16,18]
PLL4_C4 5 GCLK[7,9,17,19]
5 This only applies to 10M16, 10M25, 10M40, and 10M50 devices.