Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Document Table of Contents

5.1. ALTCLKCTRL IP Core Parameters

Table 13.   ALTCLKCTRL IP Core Parameters for Intel® MAX® 10 Devices This table lists the IP core parameters applicable to Intel® MAX® 10 devices.
Parameter Value Description
How do you want to use the ALTCLKCTRL For global clock, or For external path

Specify the ALTCLKCTRL buffering mode. You can select from the following modes:

  • For global clock—Allows a clock signal to reach all parts of the chip with the same amount of skew; you can select input port clkselect to switch between the four clock inputs.
  • For external path—Represents the clock path from the outputs of the PLL to the dedicated clock output pins; only one clock output is accepted.
How many clock inputs would you like? 1, 2, 3, or 4

Specify the number of input clock sources for the clock control block. You can specify up to four clock inputs.

You can change the number of clock inputs only if you choose For global clock option.

Create ‘ena’ port to enable or disable the clock network driven by this buffer On or Off Turn on this option if you want to create an active high clock enable signal to enable or disable the clock network.
Ensure glitch-free switchover implementation On or Off

Turn on this option to implement a glitch-free switchover when you use multiple clock inputs.

You must ensure the currently selected clock is running before switching to another source. If the selected clock is not running, the glitch-free switchover implementation will not be able to switch to the new clock source.

By default, the clkselect port is set to 00. A clock must be applied to inclk0x for the values on the clkselect ports to be read.