Intel® Arria® 10 FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your Intel® FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

User Guides / Device Overview / Device Datasheet / Application Notes

Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

Intel Arria 10 Device Datasheet

Intel Arria 10 Device Overview

Intel Arria 10 GX/GT Device Errata and Design Recommendations

Intel Arria 10 Transceiver PHY User Guide

Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel Arria 10, and Intel® Stratix® 10 Devices

Intel FPGA I/O Phase-Locked Loop (Intel FPGA IOPLL) IP Core User Guide

Intel FPGA Chip ID IP Cores User Guide

Intel Arria 10 External Memory Interfaces IP User Guide

Intel Arria 10 External Memory Interfaces IP Design Example User Guide

Intel Arria 10 External Memory Interface IP Core Release Notes

Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide

Intel FPGA Voltage Sensor IP Core User Guide

Early Power Estimator for Intel Arria 10 FPGAs User Guide

Intel FPGA Temperature Sensor IP Core User Guide

Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines

Intel FPGA Parallel Flash Loader IP Core User Guide

Intel FPGA ASMI Parallel II IP Core User Guide

Intel FPGA ASMI Parallel IP Core User Guide

Intel FPGA Remote Update IP Core User Guide

PHYLite Design Implementation Guidelines

AN 556: Using the Design Security Features in Intel FPGAs

AN 496: Using the Internal Oscillator IP Core

AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families

AN 756: Intel FPGA GPIO to Intel FPGA

AN 711: Power Reduction Features in Intel Arria 10 Devices

AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel Arria 10 Devices

AN 737: SEU Detection and Recovery in Intel Arria 10 Devices

AN 738: Intel Arria 10 Device Design Guidelines

AN 742: PMBus SmartVID Controller Reference Designs

AN 370: Using the Intel FPGA Serial Flash Loader with the Intel® Quartus® Prime Software

Design Examples
External Memory Interface Version

Intel Arria 10 DDR3 x40 with EMIF Debug Toolkit

15.0

Training and Videos

External Memory Interface

Guide for New External Memory Interface (EMIF) Spec Estimator

External Memory Interface Device Selector Tutorial

Introducing BluePrint Platform Designer for External Memory Interface Designs Part 1 of 2

Introducing BluePrint Platform Designer for External Memory Interface Designs Part 2 of 2

DDR4 Ping Pong PHY

How to Generate Intel Arria 10 EMIF Example Design

Creating Multiple Intel Arria 10 Memory Designs with Qsys

Simulating an Intel Arria 10 External Memory Interface

Intel Arria 10 FPGA & SoC EMIF

How to Implement Package Deskew in External Memory Interface Design in Intel Stratix 10 and Intel Arria 10

Board Timing for Intel Arria 10 EMIF IP

Implementing Over Constraint in Intel Arria 10 External Memory Interface

Automated Check of Intel FPGA External Memory Interfaces Board Layout Guidelines

Intel Arria 10 External Memory Interface Toolkit

Intel Arria 10 EMIF Example Traffic Generator

Using the Soft Nios® Processor to Debug Intel Arria 10 External Memory Interfaces

Intel Arria 10 External Memory Interface Read and Write 2-D Eye Diagram

External Memory Interface Driver Margining Part 1

External Memory Interface Driver Margining Part 2

How to Build RLDRAM3 EMIF Design for Arria 10 Development Kit and Test the Calibration Status Using EMIF Toolkit

Intel FPGA PHYLite Demo Part 1

Intel FPGA PHYLite Demo Part 2

Building Parallel Interfaces with Intel FPGA PHYLite IP

How to Perform Group Pin Placement for PHYLite IP

Generating PHYLite Example Design Simulation in ModelSim* in 16.1 with Intel Arria 10

How to Create the OCT Block for Calibrated Termination I/O Buffer in Intel FPGA PHYLIte IP

How to Estimate Inte Arria 10 / Intel Stratix 10 PHYLite Input and Output Path Latency

How to Configure A10 /S10 Intel FPGA PHYLite Input and Output Delay Constraints

How to Configure PHYLite IP Dynamic Reconfiguration Timing Settings

Introduction to Memory Interfaces IP in Intel Arria 10 & Intel Stratix 10 Devices

Integrating Memory Interfaces IP in Intel Arria 10 Devices

Verifying Memory Interfaces IP in Intel Arria 10 Devices

On-Chip Debugging of Memory Interfaces IP in Intel Arria 10 Devices