Arria® 10 FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

Agilex™ 7 Design Hub Stratix® 10 Developer Center Arria® 10 Developer Center Cyclone® 10 Developer Center MAX® 10 Developer Center

1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Arria® 10 Core Fabric and General Purpose I/Os Handbook

Arria® 10 Device Datasheet

Arria® 10 Device Overview

Arria® 10 GX/GT Device Errata and Design Recommendations

Arria® 10 Transceiver PHY User Guide

Power Sequencing Considerations for Cyclone® 10 GX, Arria® 10, and Stratix® 10 Devices

FPGA I/O Phase-Locked Loop (FPGA IOPLL) IP Core User Guide

FPGA Chip ID IP Cores User Guide

Arria® 10 External Memory Interfaces IP User Guide

Arria® 10 External Memory Interfaces IP Design Example User Guide

Arria® 10 External Memory Interface IP Core Release Notes

Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide

FPGA Voltage Sensor IP Core User Guide

Early Power Estimator for Arria® 10 FPGAs User Guide

FPGA Temperature Sensor IP Core User Guide

Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

FPGA Parallel Flash Loader IP Core User Guide

FPGA ASMI Parallel II IP Core User Guide

FPGA ASMI Parallel IP Core User Guide

FPGA Remote Update IP Core User Guide
PHYLite Design Implementation Guidelines

AN 556: Using the Design Security Features in FPGAs

AN 496: Using the Internal Oscillator IP Core

AN 522: Implementing Bus LVDS Interface in Supported FPGA Device Families
AN 756: FPGA GPIO to FPGA

AN 711: Power Reduction Features in Arria® 10 Devices

AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Arria® 10 Devices

AN 737: SEU Detection and Recovery in Arria® 10 Devices

AN 738: Arria® 10 Device Design Guidelines

AN 742: PMBus SmartVID Controller Reference Designs

AN 370: Using the FPGA Serial Flash Loader with the Quartus® Prime Software
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Design Examples

Arria® 10 Internal Temperature Sensor Reference Design

Arria® 10 IOPLL Multiple Profile Reconfiguration
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Training and Videos
Mitigating Single Event Upsets in Altera® Arria® 10 and Altera Cyclone® 10 GX Devices
SEU Mitigation in Altera® FPGA Devices: Hierarchy Tagging
Partial Reconfiguration for Altera® FPGA Devices: Design Guidelines & Host Requirements
Partial Reconfiguration for Altera® FPGA Devices: Introduction & Project Assignments
Partial Reconfiguration for Altera® FPGA Devices: Output Files & Demonstration
Partial Reconfiguration for Altera® FPGA Devices: PR Host IP & Implementations
Generation 10 Transceiver Clocking
Transceiver Basics for 20 nm and 28 nm Devices
Arria® 10 Device Videos
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Development Kits

Arria® 10 GX FPGA Development Kit

Arria® 10 GX Transceiver Signal Integrity Development Kit
Arria® 10 SoC Development Kit

Programmable Acceleration Card (PAC) with Arria® 10 GX FPGA
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2. Interface Protocols

Documentation

User Guides
External Memory Interface

Arria® 10 External Memory Interfaces IP User Guide

Arria® 10 External Memory Interfaces IP Design Example User Guide

FPGA PHYLite for Parallel Interfaces IP Core User Guide
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User Guides / Application Notes
Ethernet

FPGA Triple-Speed Ethernet IP Core User Guide

FPGA Low Latency Ethernet 10G MAC User Guide

Arria® 10 25 Gbps Ethernet IP Core User Guide

50 Gbps Ethernet IP Core User Guide

Low Latency 100-Gbps Ethernet IP Core User Guide

Low Latency 40-Gbps Ethernet IP Core User Guide

Arria® 10 Transceiver PHY User Guide

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design

AN 735: FPGA Low Latency Ethernet 10G MAC IP Core Migration Guidelines

AN 808: Migration Guidelines from Arria® 10 to Stratix® 10 for 10G Ethernet Subsystem

AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC IP Core in Arria® 10 Devices

AN 699: Using the FPGA Ethernet Design Toolkit

AN 701: Scalable Low Latency Ethernet 10G MAC Using Arria® 10 1G/10G PHY

AN 794: Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

AN 744: Scalable Triple Speed Ethernet Reference Design for Arria® 10 Devices
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User Guides
PCI Express*

Arria® 10 Hard IP for PCI Express* IP Cores

Arria® 10 and Cyclone® 10 Avalon® -ST Interface for PCIe* User Guide

Arria® 10 or Cyclone® 10 Avalon -MM DMA Interface for PCIe Solutions User Guide

Arria® 10 and Cyclone® 10 Avalon -MM Interface for PCIe User Guide

Arria® 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide

Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide
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Application Notes / Reference Design User Guide

PCI Express: Migrating to Stratix® 10 from Arria® 10 for the Avalon-MM and Avalon-MM DMA Interfaces

PCI Express DMA Reference Design Using External Memory

PCI Express High Performance Reference Design
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User Guides / Application Notes
Other Serial IP

JESD204B IP Core User Guide

AN 753: FPGA JESD204B IP Core and ADI AD6676 Hardware Checkout Report

AN 749: FPGA JESD204B IP Core and ADI AD9144 Hardware Checkout Report

AN 809: SerialLite III IP Core Feature and Interface Differences Between Stratix® 10, Arria® 10, and Stratix® V

Interlaken IP Core Feature and Interface Differences Between Stratix® 10, Arria® 10, and Stratix® V Devices
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User Guides
Digital Signal Processing (DSP)

FPGA_CORDIC IP Core User Guide

BCH IP Core USer Guide

FFT IP Core User Guide

FIR II IP Core User Guide

Viterbi IP Core User Guide

Turbo IP Core User Guide

Floating-Point IP Cores User Guide

High-Speed Reed-Solomon IP Core User Guide

Reed-Solomon II IP Core User Guide

NCO IP Core User Guide

Random Number Generator IP Core User Guide
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User Guides
Embedded

Embedded Peripherals IP User Guide
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User Guides
Audio and Video
FPGA SDI II IP Core User Guide
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Design Examples
External Memory Interface Version

Arria® 10 DDR3 x40 with EMIF Debug Toolkit

15.0
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Design Example User Guides
Ethernet

25G Ethernet Design Example User Guide

50G Ethernet Design Example User Guide

Low Latency 100G Ethernet Design Example User Guide

Low Latency 40G Ethernet Example Design User Guide

FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Arria® 10 Devices
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Design Example User Guides
PCI Express*

Arria® 10 and Cyclone® 10 Avalon-ST Hard IP for PCIe Design Example User Guide

Arria® 10 and Cyclone® 10 Avalon -MM Interface for PCIe Design Example User Guide
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Design Example User Guides
Other Serial IP

JESD204B IP Core Design Example User Guide

FPGA JESD204B Design Example User Guide for Arria® 10 Devices
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Training and Videos
External Memory Interface

Guide for New External Memory Interface (EMIF) Spec Estimator

External Memory Interface Device Selector Tutorial

Introduction to Memory Interfaces IP in Altera® FPGA Devices

Integrating Memory Interfaces IP in Altera® FPGA Devices

Verifying Memory Interfaces IP in Altera® FPGA Devices

On-Chip Debugging of Memory Interfaces IP in Altera® FPGA Devices
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FPGA Wiki
External Memory Interface

Arria® 10 EMIF Simulation Guidance

Arria® 10 Debugging Multiple EMIFs

Arria® 10 EMIF Debug GUI
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3. Design Planning

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Getting Started User Guide: Quartus® Prime Pro Edition

Platform Designer User Guide (Quartus® Prime Pro Edition)

DSP Builder for FPGAs

AN 738: Arria® 10 Device Design Guidelines

AN 763: Arria® 10 SoC Device Design Guidelines
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Training and Videos

Fast & Easy I/O System Design with Interface Planner
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4. Design Entry

Documentation

The Quartus® Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

The Quartus® Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these template, refer to the "Using Provided HDL Templates" section of the Quartus® Prime Pro Edition Handbook.

The Quartus® Prime design software also comes with High Level Synthesis Compiler which synthesizes a C++ function into an RTL implementation that is optimized for FPGA products.

User Guides / Device Overview / Device Datasheet / White Paper

Design Recommendations User Guide: Quartus Prime Pro Edition

High Level Synthesis Compiler Getting Started Guide

High Level Synthesis Compiler User Guide

Platform Designer User Guide: Quartus® Prime Pro Edition

Scripting User Guide: Quartus® Prime Pro Edition

Advanced Synthesis Cookbook

High Level Synthesis Compiler Best Practices Guide

High Level Synthesis Compiler Reference Manual

High Level Synthesis Compiler Release Notes

Advanced Synthesis Cookbook

Applying the Benefits of Network on a Chip Architecture to FPGA System Design
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Design Examples

Platform Designer Design Examples

Platform Designer Pro Tutorial Design Example for Arria® 10 FPGA

Platform Designer Tutorial Design Example for Arria® 10 FPGA

Platform Designer Tutorial Design Example

VHDL Examples

Verilog Examples

Quartus® Design Examples
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Training and Videos

Using the Altera® Quartus® Prime Standard Edition Software: An Introduction

Introduction to Verilog HDL

Verilog HDL Basics

Advanced Verilog HDL Design Techniques

SystemVerilog with Quartus® Prime Design Software

VHDL Basics

Introduction to Platform Designer

Platform Designer in the Altera® Quartus® Prime Pro Edition Software

Creating a System Design with Platform Designer: Getting Started

Using the Altera® Quartus Prime Pro Edition Synthesis Engine
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Software Downloads

Download center for all versions of the Quartus® Prime software
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5. Simulation and Verification

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Quartus® Prime Standard Edition User Guide: Third-party Simulation

Quartus® Prime Pro Edition User Guide: Third-party Simulation

Simulation Quick-Start for ModelSim*-Intel FPGA Edition

Avalon® Verification IP Suite User Guide

FPGA Software Installation and Licensing

Simulating the a8251 Model with the Visual IP Software

Simulating the a8259 Model with the Visual IP Software

Simulating the Reed-Solomon Model with the Visual IP Software

Simulating the Turbo Encoder/Decoder Model with the Visual IP Software
AN 811: Using the Avery BFM for PCI Express* Gen3x16 Simulation on Stratix 10 Devices

AN 720: Simulating the ASMI Block in Your Design

AN 351: Simulating Nios® II Processor Designs

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

Simulating FPGA Devices with IBIS Models
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Training and Videos

Advanced System Design Using Platform Designer: System Verification with System Console

Advanced System Design Using Platform Designer: Component & System Simulation

Verifying Memory Interfaces IP in Altera® FPGA Devices
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FPGA Wiki

Simulating Designs with Lower-Level Qsys Systems

Arria® 10 EMIF Simulation Guidance
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Software Downloads

Quartus® Prime Software
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6. Implementation and Optimization

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Compiler User Guide: Quartus® Prime Pro Edition

Design Optimization User Guide: Quartus® Prime Pro Edition

Third-party Synthesis User Guide: Quartus® Prime Pro Edition

Design Constraints User Guide: Quartus® Prime Pro Edition

Block-Based Design User Guide: Quartus® Prime Pro Edition

Partial Reconfiguration User Guide: Quartus® Prime Pro Edition

DSP Builder for FPGAs

AN 738: Arria® 10 Device Design Guidelines
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Training and Videos

Design Block Reuse in the Altera® Quartus® Prime Pro Software

Incremental Block-Based Compilation in the Altera® Quartus® Prime Pro Software: Design Partitioning

Incremental Block-Based Compilation in the Altera® Quartus® Prime Pro Software: Introduction

Incremental Block-Based Compilation in the Altera® Quartus® Prime Pro Software: Timing Closure & Tips
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7. Timing Analysis

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Timing Analysis Overview

Timing Analyzer User Guide: Quartus® Prime Pro Edition

Quartus® II Scripting Reference Manual

SDC and TimeQuest API Reference Manual

Quartus® Prime Timing Analyzer Cookbook

AN 366: Understanding I/O Output Timing for FPGA Devices

AN 471: High-Performance FPGA PLL Analysis with TimeQuest

AN 433: Constraining and Analyzing Source-Synchronous Interfaces

AN 775: I/O Timing Information Generation Guidelines
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Training and Videos
Altera® Quartus® Prime Pro Software Timing Analysis – Part 1: Timing Analyzer
Altera® Quartus® Prime Pro Software Timing Analysis – Part 2: SDC Collections
Altera® Quartus® Prime Pro Software Timing Analysis – Part 3: Clock Constraints
Altera® Quartus® Prime Pro Software Timing Analysis – Part 4: I/O Interfaces
Altera® Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions
Altera® FPGAs Timing Analysis: Lecture
Altera® FPGAs Timing Analysis: Hands-On Labs
Altera® FPGA Timing Closure: Lecture
Altera® FPGA Timing Closure: Hands-On Lab
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FPGA Wiki

Source Synchronous Interfaces between FPGAs

Source Synchronous Analysis with TimeQuest

Constraining Edge Aligned Source Synch input interfaces in TimeQuest

Constraining Center Aligned Source Synchronous Input Interfaces in TimeQuest
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8. On-Chip Debug

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Programmer User Guide: Quartus® Prime Pro Edition

Analyzing and Debugging Designs with System Console

Design Debugging Using In-System Sources and Probes

Debug Tools User Guide: Quartus® Prime Pro Edition

FPGA Virtual JTAG (FPGA_virtual_jtag) IP Core User Guide

Analyzing and Debugging Designs with System Console

FPGA-Adaptive Software Debug and Performance Analysis

System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug

ByteBlaster II Download Cable User Guide

FPGA USB Download Cable User Guide

FPGA Download Cable II User Guide

EthernetBlaster Communications Cable User Guide

BSDL Support

AN 827: Unified Tool for Generating Programming Files

AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems, Design files

AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer

AN 799: Quick Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile

AN 693: Remote Hardware Debugging over TCP/IP for FPGA SoC

AN 541: SerialLite II Hardware Debugging Guide

AN 543: Debugging Nios® II Software Using the Lauterbach Debugger

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

AN 624: Debugging with System Console over TCP/IP
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Design Examples

Arria® 10 DDR3 x40 with EMIF Debug Toolkit

Debugging with System Console over TCP/IP (SCTCP) Design Example
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Training and Videos

Debugging JTAG Chain Integrity

On-Chip Debugging of Memory Interfaces IP in Altera® FPGA Devices
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FPGA Wiki

Development Boards and Kits

System Console

Arria® 10 EMIF Debug GUI

Arria® 10 Debugging Multiple EMIFs
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Software Downloads

FPGA Programming Software

Cable and Adapter Drivers Information

Quartus® Prime Software Stand-Alone Programmer
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