Stratix® 10 FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Stratix® 10 GX/SX Device Overview

Stratix® 10 Device Datasheet

Stratix® 10 GX, MX, and SX Device Family Pin Connection Guidelines

Stratix® 10 Clocking and PLL User Guide

Stratix® 10 Configuration User Guide

Stratix® 10 General Purpose I/O User Guide

Stratix® 10 High-Speed LVDS I/O User Guide

Stratix® 10 JTAG Boundary-Scan Testing User Guidex

Stratix® 10 Logic Array Blocks and Adaptive Logic Modules User Guide

Stratix® 10 Power Management User Guide

Stratix® 10 SEU Mitigation User Guide

Stratix® 10 Analog to Digital Converter User Guide

Stratix® 10 Device Design Guidelines

Stratix® 10 Embedded Memory User Guide

Stratix® 10 L- and H-Tile Transceiver PHY User Guide

Stratix® 10 MX (DRAM System-in-Package) Device Overview

Mailbox Client Stratix® 10 FPGA IP Core User Guide

AN 692: Power Sequencing Considerations for Agilex™, Stratix® 10, Cyclone® 10 GX and Arria® 10 and Devices

AN 766: Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

AN 778: Stratix® 10 L-Tile/H-Tile Transceiver Usage
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Training and Videos

Configuration for Stratix® 10 Devices

Stratix® 10 Transceiver Basics
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Development Kits

Stratix® 10 GX FPGA Development Kit

Stratix® 10 GX Signal Integrity Development Kit

Stratix® 10 SX SoC Development Kit
Stratix® 10 TX Signal Integrity Development Kit
Stratix® 10 MX FPGA Development Kit
Stratix® 10 DX FPGA Development Kit
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2. Interface Protocol

Documentation

User Guides
External Memory Interfaces

Stratix® 10 External Memory Interfaces IP User Guide

Stratix® 10 External Memory Interfaces IP Design Example User Guide

Stratix® 10 MX HBM2 IP User Guide

FPGA PHYLite for Parallel Interfaces IP Core User Guide
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User Guides / Application Notes
Ethernet User Guides

FPGA Triple-Speed Ethernet IP Core User Guide

FPGA Low Latency Ethernet 10G MAC User Guide

Stratix® 10 1G/2-5G/5G/10G Multi-Rate Ethernet PHY IP Core User Guide

Stratix® 10 10GBASE-KR PHY IP Core User Guide

Stratix® 10 Low Latency 40-Gbps Ethernet IP Core User Guide

Stratix® 10 Low Latency 100-Gbps Ethernet IP Core User Guide

Stratix® 10 E-Tile Transceiver PHY User Guide

Stratix® 10 H-Tile Hard IP for Ethernet IP Core User Guide

AN 735: Altera® Low Latency Ethernet 10G MAC IP Core Migration Guidelines

AN 808: Migration Guidelines from Arria® 10 to Stratix® 10 for 10G Ethernet Subsystem

AN 830: FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design
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User Guides
PCI Express*

Stratix® 10 Avalon®-MM Interface for PCIe* Solutions User Guide

Stratix® 10 Avalon-ST and Single Root I/O Virtualization (SRIOV) Interface for PCIe Solutions User Guide

Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide
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Application Notes
Other Serial IP

AN 782: Interlaken IP Core Feature and Interface Differences Between Stratix® 10, Arria® 10, and Stratix V Devices

AN 804: Implementing ADC- Stratix® 10 Multi-Link Design with JESD204B RX IP Core

AN 809: SerialLite III IP Core Feature and Interface Differences Between Stratix® 10, Arria® 10, and Stratix V
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User Guides
Transceiver PHY

Stratix® 10 L- and H-Tile Transceiver PHY User Guide
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User Guides
Digital Signal Processing (DSP)

LDPC IP Core User Guide

ALTERA_CORDIC IP Core User Guide

BCH IP Core User Guide

FFT IP Core User Guide

FIR II IP Core User Guide

Viterbi IP Core User Guide

Turbo IP Core User Guide

Fixed-Point IP Cores (ALTERA_FIXEDPOINT_FUNCTIONS) User Guide

High-Speed Reed-Solomon IP Core User Guide

NCO IP Core User Guide

Random Number Generator IP Core User Guide
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User Guides
Embedded

FPGA SDI II IP Core User Guide
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User Guides
Audio and Video

Embedded Peripherals IP User Guide
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Design Example User Guides
Ethernet

Stratix® 10 Low Latency 100G Ethernet Design Example User Guide

FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Stratix® 10 Devices

Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

Stratix® 10 H-Tile Hard IP for Ethernet Design Example User Guide
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Design Example User Guides
PCI Express*

Stratix® 10 Avalon®-MM Hard IP for PCIe* Design Example User Guide

Stratix® 10 Avalon-ST Hard IP for PCIe Design Example User Guide
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Design Example User Guides
Other Serial IP

Interlaken IP Core (2nd Generation) Design Example User Guide

FPGA JESD204B Design Example User Guide for Stratix® 10 Devices

JESD204B IP Core Design Example User Guide

SerialLite III Streaming IP Core Design Example User Guide for Stratix® 10 Devices
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Training and Videos
External Memory Interface

Guide For New External Memory Interface (EMIF) Spec Estimator

Introduction to Memory Interfaces IP in Stratix® 10 Devices

High Bandwidth Memory (HBM2) Interfaces in Stratix® 10 MX Devices: Introduction, Architecture

High Bandwidth Memory (HBM2) Interfaces in Stratix® 10 MX Devices: HBMC Features

High Bandwidth Memory (HBM2) Interfaces in Stratix® 10 MX Devices: Implementation
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Reference Designs
PCI Express*

Reference Design: Gen3x8 AVMM DMA - Stratix® 10
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3. Design Planning

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Getting Started User Guide: Quartus® Prime Pro Edition

Platform Designer User Guide: Quartus® Prime Pro Edition

DSP Builder for FPGAs

Stratix® 10 Device Design Guidelines

AN 821: Interface Planning for Stratix® 10 FPGAs
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Training and Videos

Fast & Easy I/O System Design with Interface Planner
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4. Design Entry

Documentation

The Quartus® Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

The Quartus® Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these templates, refer to the "Using Provided HDL Templates" section of the Quartus® Prime Pro Handbook.

The Quartus® Prime design software also comes with High Level Synthesis Compiler which synthesizes a C++ function into an RTL implementation that is optimized for FPGA products.

User Guides / Device Overview / Device Datasheet / White Paper

Design Recommendations User Guide: Quartus® Prime Pro Edition

High Level Synthesis Compiler Getting Started Guide

High Level Synthesis Compiler User Guide

Scripting User Guide: Quartus® Prime Pro Edition

Advanced Synthesis Cookbook

High Level Synthesis Compiler Best Practices Guide

High Level Synthesis Compiler Reference Manual

High Level Synthesis Compiler Release Notes

Applying the Benefits of Network on a Chip Architecture to FPGA System Design
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Design Examples

Platform Designer Design Examples

Platform Designer Pro Tutorial Design Example for Arria® 10 FPGA

Platform Designer Tutorial Design Example for Arria® 10 FPGA

Platform Designer Tutorial Design Example

Quartus® Design Examples
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Training and Videos

Using the Quartus® Prime Software: An Introduction

Introduction to Verilog HDL

Verilog HDL Basics

Advanced Verilog HDL Design Techniques

SystemVerilog with the Quartus® II Software

VHDL Basics

Introduction to Platform Designer

Platform Designer in the Quartus® Prime Pro Edition Software

Creating a System Design with Platform Designer: Getting Started

Using Spectra-Q Synthesis in the Quartus® Prime Software
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Software Downloads

Download center for all versions of the Quartus® Prime software
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5. Simulation and Verification

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Quartus® Prime Pro Edition User Guide: Third-party Simulation

Simulation Quick-Start for ModelSim*-Intel® FPGA Edition

Avalon® Verification IP Suite User Guide

Altera® FPGA Software Installation and Licensing

Simulating the a8251 Model with the Visual IP Software

Simulating the a8259 Model with the Visual IP Software

Simulating the Reed-Solomon Model with the Visual IP Software

Simulating the Turbo Encoder/Decoder Model with the Visual IP Software

AN 811: Using the Avery BFM for PCI Express* Gen3x16 Simulation on Stratix® 10 Devices

AN 351: Simulating Nios® II Processor Designs

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

Simulating FPGA Devices with IBIS Models
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Design Examples
Avalon® Verification IP Suite Design Example
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Training and Videos

Advanced System Design Using Qsys: System Verification with System Console

Advanced System Design Using Qsys: Component & System Simulation

Avalon® Verification Suite

Verifying Memory Interfaces IP in Stratix® 10 Devices
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FPGA Wiki

Simulating Designs with Lower-Level Qsys Systems
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Software Downloads

Quartus® Software
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6. Implementation and Optimization

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Compiler User Guide: Quartus® Prime Pro Edition

Design Optimization User Guide: Quartus® Prime Pro Edition

Third-party Synthesis User Guide: Quartus® Prime Pro Edition

Design Constraints User Guide: Quartus® Prime Pro Edition

Block-Based Design User Guide: Quartus® Prime Pro Edition

Partial Reconfiguration User Guide: Quartus® Prime Pro Edition

DSP Builder for FPGAs

Stratix® 10 High-Performance Design Handbook

Stratix® 10 Device Datasheet

Stratix® 10 Device Design Guidelines

AN 716: Hyper-Optimization for Stratix® 10 Designs

AN 715: Hyper-Pipelining for Stratix® 10 Designs
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Training and Videos

Introduction to Hyper-Retiming

Eliminating Barriers to Hyper-Retiming

Introduction to Incremental Compilation

Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Introduction

Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Design Partitioning

Advanced Optimization with Stratix® 10 FPGA Hyperflex™ Architecture

Hyper-Optimization Techniques 1: Loop Analysis and Solutions

Hyper-Optimization Techniques 2: Pre-Computation

Hyper-Optimization Techniques 3: Shannon’s Decomposition

Introduction to Hyper-Optimization

Quartus® Prime Software Hyper-Aware Design Flow

Introduction to Hyper-Pipelining

Performance Optimization with Stratix® 10 FPGA Hyperflex Architecture

Stratix® 10 Hyperflex Design: Analyzing Critical Chains

The Hyperflex FPGA Optimization Workshop

Using Fast Forward Compile for the Hyperflex Architecture
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7. Timing Analysis

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Timing Analysis Overview

Timing Analyzer User Guide (Quartus® Prime Pro Edition)

Quartus® II Scripting Reference Manual

SDC and TimeQuest API Reference Manual

Quartus® Prime Timing Analyzer Cookbook

AN 366: Understanding I/O Output Timing for Altera® Devices

AN 471: High-Performance FPGA PLL Analysis with TimeQuest

AN 433: Constraining and Analyzing Source-Synchronous Interfaces

AN 775: I/O Timing Information Generation Guidelines
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Design Examples

Timing Analyzer Design Examples
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Training and Videos
Quartus® Prime Pro Software Timing Analysis – Part 1: Timing Analyzer
Quartus® Prime Pro Software Timing Analysis – Part 2: SDC Collections
Quartus® Prime Pro Software Timing Analysis – Part 3: Clock Constraints
Quartus® Prime Pro Software Timing Analysis – Part 4: I/O Interfaces
Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions
Timing Analysis: Lecture
Timing Analysis: Hands-on Labs
FPGA Timing Closure: Lecture
FPGA Timing Closure: Hands-On Lab
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FPGA Wiki

Source Synchronous Interfaces between FPGA FPGAs

Source Synchronous Analysis with TimeQuest

Constraining Edge Aligned Source Synch input interfaces in TimeQuest

Constraining Center Aligned Source Synchronous Input Interfaces in TimeQuest
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8. On-Chip Debug

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Programmer User Guide: Quartus® Prime Pro Edition

Analyzing and Debugging Designs with System Console

Design Debugging Using In-System Sources and Probes

Debug Tools User Guide: Quartus® Prime Pro Edition

FPGA Virtual JTAG (FPGA_virtual_jtag) IP Core User Guide

Analyzing and Debugging Designs with System Console

FPGA-Adaptive Software Debug and Performance Analysis

System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug

ByteBlaster II Download Cable User Guide

FPGA USB Download Cable User Guide

FPGA Download Cable II User Guide

EthernetBlaster Communications Cable User Guide

BSDL Support

AN 827: Unified Tool for Generating Programming Files

AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems, Design files

AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer

AN 693: Remote Hardware Debugging over TCP/IP for FPGA SoC

AN 541: SerialLite II Hardware Debugging Guide

AN 543: Debugging Nios II Software Using the Lauterbach Debugger

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

AN 624: Debugging with System Console over TCP/IP
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Design Examples

Debugging with System Console over TCP/IP (SCTCP) Design Example
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Training and Videos

Debugging JTAG Chain Integrity

On-Chip Debugging of Memory Interfaces IP in Arria® 10 Devices

SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals

The Quartus® Software Debug Tools
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FPGA Wiki

Development Boards and Kits

System Console

Arria® 10 EMIF Debug GUI

Arria® 10 Debugging Multiple EMIFs
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Software Downloads

FPGA Programming Software

FPGA Jam™ STAPL Software

Cable and Adapter Drivers Information

MAX+PLUS® II Software

FPGA Legacy Software

Quartus® Prime Software Stand-Alone Programmer

FPGA Stand-Alone Programmer Software

Quartus® Prime Software
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Explore Other Developer Centers

For other design guidelines, visit the following Developer Centers: