Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

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ID 683149
Date 8/08/2022
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1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

Delivering over 10X higher memory bandwidth compared to discrete DRAM solutions, Intel® Stratix® 10 MX DRAM System-in-Package (SiP) devices meet the memory bandwidth requirements of your next-generation designs.

Intel® Stratix® 10 MX devices integrate 3D stacked High-Bandwidth DRAM Memory (HBM2) alongside a high-performance monolithic 14 nm FPGA fabric die, and multiple high-speed transceiver tiles, all inside a single flip-chip FBGA package.

This new class of device offers the highest memory bandwidth available in an FPGA, eliminating the memory bandwidth bottlenecks in high-performance systems such as datacenter, broadcast, wireline networking and high-performance computing systems. Intel® Stratix® 10 MX devices enable you to achieve the highest memory bandwidth and lowest system power, giving you the best bandwidth per watt metric.

Intel® Stratix® 10 MX devices feature several groundbreaking innovations such as the new HyperFlex® core architecture, dual mode 57.8 Gbps PAM4 / 28.9 Gbps Non-Return to Zero (NRZ) transceivers, and advanced packaging technology based on Intel’s Embedded Multi-die Interconnect Bridge (EMIB). These devices demonstrate Intel's leadership in high-performance programmable devices and our commitment to deliver the most advanced solutions to your most challenging system problems.

Important innovations in Intel® Stratix® 10 MX devices include:

  • All new Intel® Hyperflex™ core architecture delivering 2X the core performance compared to previous generation high-performance FPGAs
  • Hard HBM2 controller designed to provide the highest levels of performance
  • Intel 14 nm tri-gate (FinFET) technology
  • Heterogeneous 3D System-in-Package (SiP) technology
  • Integrated 3D stacked High-Bandwidth DRAM Memory (HBM2)
  • Monolithic core fabric with up to 2.1 million logic elements (LEs)
  • Up to 96 full duplex transceiver channels on heterogeneous 3D SiP transceiver tiles
  • Transceiver data rates up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ for chip-to-chip, chip-to-module, and backplane driving
  • Embedded eSRAM (47.25 Mbit) and M20K (20 Kb) internal SRAM memory blocks
  • Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops (PLLs)
  • Hard PCI Express* Gen3 x16 intellectual property (IP) blocks
  • Hard 100G Ethernet MAC, 100G Reed-Solomon FEC, and KP-FEC blocks
  • Hard memory controllers and PHY supporting DDR4 rates up to 2666 Mbps per pin
  • Hard fixed-point and IEEE 754 compliant hard floating-point variable precision digital signal processing (DSP) blocks with up to 6.5 TFLOP compute performance with a power efficiency of 80 GFLOP per Watt
  • Programmable clock tree synthesis for flexible, low power, low skew clock trees
  • Dedicated secure device manager (SDM) for:
    • Enhanced device configuration and security
    • AES-256, SHA-256/384 and ECDSA-256/384 encrypt/decrypt accelerators and authentication
    • Multi-factor authentication
    • Physically Unclonable Function (PUF) service and software programmable device configuration capability
  • Advanced power saving features delivering up to 70% lower core power compared to previous generation high-performance FPGAs

With these capabilities, Intel® Stratix® 10 MX devices are ideally suited for the highest memory bandwidth applications in diverse markets such as:

  • Compute and Storage—for custom servers, cloud computing and datacenter acceleration
  • Networking—for Terabit, 400G and multi-100G bridging, aggregation, packet processing and traffic management
  • Optical Transport Networks—for OTU4, 2xOTU4, 4xOTU4
  • Broadcast—for high-end studio distribution, headend encoding/decoding, edge QAM
  • Military—for radar, electronic warfare, and secure communications
  • Medical—for diagnostic scanners and diagnostic imaging
  • Test and Measurement—for protocol analyzers and application testers
  • Wireless—for next-generation 5G networks

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