Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

ID 683149
Date 8/18/2022
Public
Document Table of Contents

1.3. Intel® Stratix® 10 MX Features Summary

Table 2.   Intel® Stratix® 10 MX Device Features

Feature

Description

Core process technology

  • 14 nm Intel tri-gate (FinFET) process technology
  • SmartVID controlled core voltage, standard power devices

Low power serial transceivers

  • Up to 96 total transceivers available
  • Continuous operating range of 1 Gbps to 57.8 Gbps PAM4 / 28.9 Gbps NRZ
  • Backplane support up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ
  • Extended range down to 125 Mbps with oversampling
  • ATX transmit PLLs with user-configurable fractional synthesis capability
  • XFP, SFP+, QSFP/QSFP28, CFP/CFP2/CFP4 optical module support
  • Adaptive linear and decision feedback equalization
  • Transmit pre-emphasis and de-emphasis
  • Dynamic partial reconfiguration of individual transceiver channels
  • On-chip instrumentation (Eye Viewer non-intrusive data eye monitoring)

General purpose I/Os

  • Up to 656 total GPIO available
  • 1.6 Gbps LVDS—every pair can be configured as an input or output
  • 1333 MHz/2666 Mbps DDR4 external memory interface
  • 1067 MHz/2133 Mbps DDR3 external memory interface
  • 1.2 V to 3.0 V single-ended LVCMOS/LVTTL interfacing
  • On-chip termination (OCT)

Embedded hard IP

  • PCIe Gen1/Gen2/Gen3 complete protocol stack, x1/x2/x4/x8/x16 end point and root port
  • 100 GbE MAC, Reed-Solomon FEC hard IP, and KP-FEC hard IP
  • DDR4/DDR3 hard memory controller (RLDRAM3/QDR II+/QDR IV using soft memory controller)
  • Multiple hard IP instantiations in each device

Transceiver hard IP

  • 10GBASE-KR/40GBASE-KR4 FEC
  • 10G Ethernet PCS
  • PCI Express* PIPE interface
  • Interlaken PCS
  • Gigabit Ethernet PCS
  • Deterministic latency support for Common Public Radio Interface (CPRI) PCS
  • Fast lock-time support for Gigabit Passive Optical Networking (GPON) PCS
  • 8B/10B, 64B/66B, 64B/67B encoders and decoders
  • Custom mode support for proprietary protocols

Power management

  • SmartVID controlled core voltage, standard power devices
  • Intel® Quartus® Prime Pro Edition integrated power analysis

High performance monolithic core fabric

  • Intel® Hyperflex™ core architecture with Hyper-Registers everywhere throughout the interconnect routing and at the inputs of all functional blocks
  • Monolithic fabric minimizes compile times and increases logic utilization
  • Enhanced adaptive logic module (ALM)
  • Improved multi-track routing architecture reduces congestion and improves compile times
  • Hierarchical core clocking architecture with programmable clock tree synthesis
  • Fine-grained partial reconfiguration

Internal memory blocks

  • eSRAM—47.25 Mbit with hard ECC support
  • M20K—20 Kb with hard ECC support
  • MLAB—640 bit distributed LUTRAM

Variable precision DSP blocks

  • IEEE 754-compliant hard single-precision floating point capability
  • Supports signal processing with precision ranging from 18x19 up to 54x54
  • Native 27x27 and 18x19 multiply modes
  • 64 bit accumulator and cascade for systolic FIRs
  • Internal coefficient memory banks
  • Pre-adder/subtractor improves efficiency
  • Additional pipeline register increases performance and reduces power

Phase locked loops (PLL)

  • Fractional synthesis PLLs (fPLL) support both fractional and integer modes
  • Fractional mode with third-order delta-sigma modulation
  • Precision frequency synthesis
  • Integer PLLs adjacent to general purpose I/Os, support external memory, and LVDS interfaces, clock delay compensation, zero delay buffering

Core clock networks

  • 1 GHz fabric clocking
  • 667 MHz external memory interface clocking, supports 2666 Mbps DDR4 interface
  • 800 MHz LVDS interface clocking, supports 1600 Mbps LVDS interface
  • Programmable clock tree synthesis, backwards compatible with global, regional and peripheral clock networks
  • Clocks only synthesized where needed, to minimize dynamic power

Configuration

  • Dedicated Secure Device Manager
  • Software programmable device configuration
  • Serial and parallel flash interface
  • Configuration via protocol (CvP) using PCI Express Gen1/Gen2/Gen3
  • Fine-grained partial reconfiguration of core fabric
  • Dynamic reconfiguration of transceivers and PLLs
  • Comprehensive set of security features including AES-256, SHA-256/384, and ECDSA-256/384 accelerators, and multi-factor authentication
  • Physically Unclonable Function (PUF) service

Packaging

  • Intel Embedded Multi-die Interconnect Bridge (EMIB) packaging technology
  • Multiple devices with identical package footprints allows seamless migration across different device densities
  • 1.0 mm ball-pitch FBGA packaging
  • Lead and lead-free package options

Software and tools

  • Intel® Quartus® Prime Pro Edition design suite with new compiler and Hyper-Aware design flow
  • Fast Forward compiler to allow Intel® Hyperflex™ architecture performance exploration
  • Transceiver toolkit
  • Platform Designer system integration tool
  • DSP Builder advanced blockset
  • OpenCL™ support

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