Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

ID 683149
Date 8/18/2022
Public
Document Table of Contents

1.27. Document Revision History for the Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

Document Version Changes
2022.08.18 Made the following change:
  • Removed the details of Register state readback and writeback feature from Key Features of Intel Stratix 10 MX Devices Compared to Stratix V Devices table.
  • Removed readback and writeback feature from advatnages in Device Configuration and Secure Device Manager (SDM) section.
2022.08.08 Updated the sample ordering code and available options:
  • Updated the H-Tile maximum data rate for –2 transceiver speed grade from 26.0 Gbps to 26.6 Gbps
  • Updated the E-Tile maximum data rate (NRZ) for –1 transceiver speed grade from 30.0 Gbps to 28.9 Gbps
2020.09.28 Made the following change:
  • Added black key provisioning (-BK) devices. See the "Sample Ordering Code" figure in Available Options.
2020.03.24 Made the following change:
  • Added advanced security (-AS) devices.
2019.08.19 Made the following change:
  • Added composition details for the leaded and lead-free contact device options.
2019.03.13 Made the following changes:
  • Updated maximum transceiver data rates from 30 Gbps NRZ to 28.9 Gbps NRZ.
  • Updated data in the " Intel® Stratix® 10 MX Family Plan—Interconnects, PLLs, Hard IP, and HBM2 (part 2)" table.
2019.02.15 Made the following changes:
  • Changed the number of eSRAM memory block to 47.25 Mbit and the number of embedded memory to 94.5 Mbits.
  • Changed the number of maximum transceiver data rate to 57.8 Gbps.
  • Removed the descriptions of the Hard Processor System (HPS) block.
  • Removed the MX 1100 density device from family and package plans.
2018.08.09 Made the following changes:
  • Changed the direction arrow from the coefficient registers block in the "DSP Block: High Precision Fixed Point Mode" figure.
  • Changed the descriptions for the core process technology and power management features in the " Intel® Stratix® 10 MX Device Features" table.
  • Changed the power option description in the "Sample Ordering Code and Available Options for Intel® Stratix® 10 MX Devices" figure.
  • Changed the description of the SmartVID in the "Power Management" section.
2018.04.18 Made the following change:
  • Changed the description of the logic densities in the "Sample Ordering Code and Available Options for Intel® Stratix® 10 MX Devices" figure.
2018.03.05 Made the following change:
  • Changed the number of eSRAM banks per channel to 42 in the "Internal Embedded Memory" section.
2018.02.27 Made the following change:
  • Corrected the package body size for the F2597 package in the " Intel® Stratix® 10 MX Package Plan" table.
2017.10.30 Made the following changes:
  • Changed the description for the Embedded Memory (M20K) feature in the "Key Features of Intel® Stratix® 10 MX Devices Compared to Stratix V Devices" table.
  • Changed the number of 18x19 multipliers in the "Key Features of Intel® Stratix® 10 MX Devices Compared to Stratix V Devices" table.
  • Changed the total number of General purpose I/Os available in the " Intel® Stratix® 10 MX Device Features" table.
  • Changed the resource availabilities for the MX 1650 and MX2100 devices in the " Intel® Stratix® 10 MX Family Plan—FPGA Core (part 1)" table.
  • Changed the maximum GPIOs and Maximum XCVR availabilities for the MX 1650 and MX 2100 devices in the " Intel® Stratix® 10 MX Family Plan—Interconnects, PLLs, Hard IP, and HBM2 (part 2)" table.
  • Changed the resource counts for the F2597 package in the " Intel® Stratix® 10 MX Package Plan" table.
2017.07.17 Initial release.

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