1.7. Intel® Hyperflex™ Core Architecture
Intel® Stratix® 10 MX devices are based on a monolithic core fabric featuring the new Intel® Hyperflex™ core architecture. The Intel® Hyperflex™ core architecture delivers 2X the clock frequency performance and up to 70% lower power compared to previous generation high-end FPGAs. Along with this performance breakthrough, the Intel® Hyperflex™ core architecture delivers a number of advantages including:
- Higher Throughput—Capitalizes on 2X core clock frequency performance to obtain throughput breakthroughs
- Improved Power Efficiency—Uses reduced IP size, enabled by Intel® Hyperflex™ , to consolidate designs which previously spanned multiple devices into a single device, thereby reducing power by up to 70% versus previous generation devices
- Greater Design Functionality—Uses faster clock frequency to reduce bus widths and reduce IP size, freeing up additional FPGA resources to add greater functionality
- Increased Designer Productivity—Boosts performance with less routing congestion and fewer design iterations using Hyper-Aware design tools, obtaining greater timing margin for more rapid timing closure
In addition to the traditional user registers found in the Adaptive Logic Modules (ALM), the Intel® Hyperflex™ core architecture introduces additional bypassable registers everywhere throughout the fabric of the FPGA. These additional registers, called Hyper-Registers are available on every interconnect routing segment and at the inputs of all functional blocks.
The Hyper-Registers enable the following key design techniques to achieve the 2X core performance increases:
- Fine grain Hyper-Retiming to eliminate critical paths
- Zero latency Hyper-Pipelining to eliminate routing delays
- Flexible Hyper-Optimization for best-in-class performance
By implementing these techniques in your design, the Hyper-Aware design tools automatically make use of the Hyper-Registers to achieve maximum core clock frequency.