Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

ID 683149
Date 8/18/2022
Public
Document Table of Contents

1.2. Innovations in Intel® Stratix® 10 MX Devices

Intel® Stratix® 10 MX devices deliver many significant improvements over the previous generation high-performance Stratix® V FPGAs.

Table 1.   Key Features of Intel® Stratix® 10 MX Devices Compared to Stratix® V Devices
Feature Stratix® V FPGAs Intel® Stratix® 10 MX Devices
Core fabric process technology 28 nm TSMC (planar transistor) 14 nm Intel tri-gate (FinFET)
Core architecture Conventional core architecture with conventional interconnect Intel® Hyperflex™ core architecture with Hyper-Registers in the interconnect
Core performance 500 MHz 1 GHz
Power dissipation 1x As low as 0.3x
Logic density 952 KLE (monolithic) 2,100 KLE (monolithic)
Integrated 3D stacked HBM2 DRAM memory None Up to 16 GB density / 512 GByte per second bandwidth with 2 HBM2 DRAM stacks
Embedded memory (eSRAM) None 94.5 Mbits
Embedded memory (M20K) 52 Mbits 134 Mbits
18x19 multipliers 3,926
Note: Multiplier is 18x18 in Stratix® V devices.
7,920
Note: Multiplier is 18x19 in Intel® Stratix® 10 MX devices.
Floating point DSP capability Up to 1 TFLOP, requires soft floating point adder and multiplier Up to 6.5 TFLOP, hard IEEE 754 compliant single precision floating point adder and multiplier
Maximum transceivers 66 96
Maximum transceiver data rate (chip-to-chip) 28.05 Gbps

Dual mode 57.8 Gbps PAM4 / 28.9 Gbps NRZ

Maximum transceiver data rate (backplane) 12.5 Gbps Dual mode 57.8 Gbps PAM4 / 28.9 Gbps NRZ
Hard memory controller None

DDR4 @ 1333 MHz/2666 Mbps

DDR3 @ 1067 MHz/2133 Mbps

Hard protocol IP PCIe* Gen3 x8

PCIe Gen3 x16

100G Ethernet MAC, 100G Reed-Solomon FEC hard IP, and KP-FEC hard IP
Core clocking and PLLs Global, quadrant and regional clocks supported by fractional-synthesis fPLLs Programmable clock tree synthesis supported by fractional synthesis fPLLs and integer IO PLLs

These innovations result in the following improvements:

  • Improved Core Logic Performance: The Intel® Hyperflex™ core architecture combined with Intel 14-nm Tri-Gate technology allows Intel® Stratix® 10 MX devices to achieve 2X the core performance compared to the previous generation
  • Lower Power Intel® Stratix® 10 MX devices use up to 70% lower power compared to the previous generation, enabled by Intel 14 nm tri-gate technology, the Intel® Hyperflex™ core architecture, and optional power savings features built into the architecture
  • Higher Density: Intel® Stratix® 10 MX devices offer over two times the level of integration, with up to 2,100K logic elements (LEs) in a monolithic fabric, 94.5 Mbits of embedded eSRAM blocks, over 134 Mbits of embedded M20K memory blocks, and 7,920 18x19 multipliers
  • Improved Transceiver Performance: With up to 96 transceiver channels implemented in heterogeneous 3D SiP transceiver tiles, Intel® Stratix® 10 MX devices support data rates up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ for chip-to-chip and backplane driving with signal conditioning circuits capable of equalizing over 30 dB of system loss
  • Improved DSP Performance: The variable precision DSP block in Intel® Stratix® 10 MX devices features hard fixed and floating point capability, with up to 6.5 TFLOP IEEE754 single-precision floating point performance
  • Additional Hard IP: Intel® Stratix® 10 MX devices include many more hard IP blocks than previous generation devices, with a hard memory controller included in each bank of 48 general purpose IOs, hard PCS, PCIe Gen3x16 full protocol stack, 100 GbE MAC, Reed-Solomon FEC hard IP, and KP-FEC hard IP to support the transceivers
  • Enhanced Core Clocking: Intel® Stratix® 10 MX devices feature programmable clock tree synthesis; clock trees are only synthesized where needed, increasing the flexibility and reducing the power dissipation of the clocking solution
  • Additional Core PLLs: The core fabric in Intel® Stratix® 10 MX devices is supported by both integer IO PLLs and fractional synthesis fPLLs, resulting in a greater total number of PLLs than the previous generation

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