Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

ID 683149
Date 8/18/2022
Public
Document Table of Contents

1.9. Intel® Stratix® 10 MX Transceivers

Intel® Stratix® 10 MX devices offer up to 96 total full-duplex transceiver channels. These channels provide continuous data rates from 125 Mbps to 57.8 Gbps PAM4 / 28.9 Gbps NRZ for chip-to-chip, chip-to-module, and backplane applications. For longer-reach backplane driving applications, advanced adaptive equalization circuits are used to equalize over 30 dB of system loss.

All transceiver channels feature a dedicated Physical Medium Attachment (PMA) and a hardened Physical Coding Sublayer (PCS).

  • The PMA provides primary interfacing capabilities to physical channels.
  • The PCS typically handles encoding/decoding, word alignment, and other pre-processing functions before transferring data to the FPGA core fabric.

Within each transceiver tile, the transceivers are arranged in four banks of six PMA-PCS groups. A wide variety of bonded and non-bonded data rate configurations are possible within each bank, and within each tile, using a highly configurable clock distribution network.

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