Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

ID 683149
Date 8/18/2022
Public
Document Table of Contents

1.8. Heterogeneous 3D SiP Transceiver Tiles

Intel® Stratix® 10 MX devices feature power efficient, high bandwidth, low latency transceivers. The transceivers are implemented on heterogeneous 3D System-in-Package (SiP) transceiver tiles, each containing 24 full-duplex transceiver channels. In addition to providing a high-performance transceiver solution to meet current connectivity needs, this allows for future flexibility and scalability as data rates, modulation schemes, and protocol IPs evolve.

Figure 10. Monolithic Core Fabric, Heterogeneous 3D SiP Transceiver Tiles, Stacked HBM2 DRAM Memory

Each transceiver tile contains:

  • 24 full-duplex transceiver channels (PMA and PCS)
  • Reference clock distribution network
  • Transmit PLLs
  • High-speed clocking and bonding networks
  • PCI Express* , 100G Ethernet MAC, 100G Reed-Solomon FEC, and KP-FEC hard IP
Figure 11. Heterogeneous 3D SiP Transceiver Tile Architecture

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