Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

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ID 683149
Date 8/18/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview x
1.1. Intel® Stratix® 10 MX Devices 1.2. Innovations in Intel® Stratix® 10 MX Devices 1.3. Intel® Stratix® 10 MX Features Summary 1.4. Intel® Stratix® 10 MX Block Diagram 1.5. Intel® Stratix® 10 MX Family Plan 1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.7. Intel® Hyperflex™ Core Architecture 1.8. Heterogeneous 3D SiP Transceiver Tiles 1.9. Intel® Stratix® 10 MX Transceivers 1.10. PCI Express Gen1/Gen2/Gen3 Hard IP 1.11. 100G Ethernet MAC, Reed-Solomon FEC Hard IP, and KP-FEC Hard IP 1.12. 10G Ethernet Hard IP 1.13. Interlaken PCS Hard IP 1.14. External Memory and General Purpose I/O 1.15. Adaptive Logic Module (ALM) 1.16. Core Clocking 1.17. Fractional Synthesis PLLs and I/O PLLs 1.18. Internal Embedded Memory 1.19. Variable Precision DSP Block 1.20. Power Management 1.21. Device Configuration and Secure Device Manager (SDM) 1.22. Device Security 1.23. Configuration via Protocol Using PCI Express* 1.24. Partial and Dynamic Reconfiguration 1.25. Fast Forward Compile 1.26. Single Event Upset (SEU) Error Detection and Correction 1.27. Document Revision History for the Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1.5. Intel® Stratix® 10 MX Family Plan x
1.5.1. Available Options
1.9. Intel® Stratix® 10 MX Transceivers x
1.9.1. PMA Features 1.9.2. PCS Features
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory

Intel® Stratix® 10 MX devices integrate 3D stacked High-Bandwidth DRAM Memory (HBM2) alongside a high-performance monolithic 14 nm FPGA fabric die, and multiple high-speed transceiver tiles, all inside a single flip-chip FBGA package.

This results in a “near memory” implementation where the high-density stacked DRAM is integrated very close to the FPGA in the same package. In this configuration the in-package memory is able to deliver up to 512 GByte/s of total aggregate bandwidth which represents over a 10X increase in bandwidth compared to traditional “far memory” implemented in separate devices on the board. A near memory configuration also reduces system power by reducing traces between the FPGA and memory, while also reducing board area.

Figure 7. Heterogeneous 3D Stacked HBM2 DRAM Architecture

Intel® Stratix® 10 MX devices integrate two 3D stacked HBM2 DRAM memories inside the package. Each of these DRAM stacks has:

  • 4 GB or 8 GB total density
  • 256 GB per second total aggregate bandwidth
  • 8 independent channels, each 128 bits wide, or 16 independent pseudo channels, each 64 bits wide (in pseudo channel mode)
  • Data transfer rates up to 2 Gbps, per signal, between core fabric and HBM2 DRAM
  • Half-rate transfer to core fabric

Intel® Stratix® 10 MX devices use embedded hard memory controllers to access the HBM2 DRAM.

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