Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

ID 683149
Date 8/18/2022
Public
Document Table of Contents

1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory

Intel® Stratix® 10 MX devices integrate 3D stacked High-Bandwidth DRAM Memory (HBM2) alongside a high-performance monolithic 14 nm FPGA fabric die, and multiple high-speed transceiver tiles, all inside a single flip-chip FBGA package.

This results in a “near memory” implementation where the high-density stacked DRAM is integrated very close to the FPGA in the same package. In this configuration the in-package memory is able to deliver up to 512 GByte/s of total aggregate bandwidth which represents over a 10X increase in bandwidth compared to traditional “far memory” implemented in separate devices on the board. A near memory configuration also reduces system power by reducing traces between the FPGA and memory, while also reducing board area.

Figure 7. Heterogeneous 3D Stacked HBM2 DRAM Architecture

Intel® Stratix® 10 MX devices integrate two 3D stacked HBM2 DRAM memories inside the package. Each of these DRAM stacks has:

  • 4 GB or 8 GB total density
  • 256 GB per second total aggregate bandwidth
  • 8 independent channels, each 128 bits wide, or 16 independent pseudo channels, each 64 bits wide (in pseudo channel mode)
  • Data transfer rates up to 2 Gbps, per signal, between core fabric and HBM2 DRAM
  • Half-rate transfer to core fabric

Intel® Stratix® 10 MX devices use embedded hard memory controllers to access the HBM2 DRAM.

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