Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

ID 683149
Date 8/18/2022
Public
Document Table of Contents

1.26. Single Event Upset (SEU) Error Detection and Correction

Intel® Stratix® 10 MX devices offer robust SEU error detection and correction circuitry. The detection and correction circuitry includes protection for Configuration RAM (CRAM) programming bits and user memories. The CRAM is protected by a continuously running parity checker circuit with integrated ECC that automatically corrects one or two bit errors and detects higher order multibit errors.

The physical layout of the CRAM array is optimized to make the majority of multi-bit upsets appear as independent single-bit or double-bit errors which are automatically corrected by the integrated CRAM ECC circuitry. In addition to the CRAM protection, user memories also include integrated ECC circuitry and are layout optimized for error detection and correction.

The SEU error detection and correction hardware is supported by both soft IP and the Intel® Quartus® Prime software to provide a complete SEU mitigation solution. The components of the complete solution include:

  • Hard error detection and correction for CRAM and user eSRAM and M20K memory blocks
  • Optimized physical layout of memory cells to minimize probability of SEU
  • Sensitivity processing soft IP that reports if CRAM upset affects a used or unused bit
  • Fault injection soft IP with the Intel® Quartus® Prime software support that changes state of CRAM bits for testing purposes
  • Hierarchy tagging in the Intel® Quartus® Prime software
  • Triple Mode Redundancy (TMR) used for the Secure Device Manager and critical on-chip state machines

In addition to the SEU mitigation features listed above, the Intel 14 nm tri-gate process technology used for Intel® Stratix® 10 MX devices is based on FinFET transistors which have reduced SEU susceptibility versus conventional planar transistors.

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