ID
683244
Date
6/12/2017
Public
1. Interlaken IP Core Feature and Interface Differences
Interlaken is a high-speed serial communication protocol for chip-to-chip packet transfers at rates from 25 Gbps to 300 Gbps. Intel® FPGA's Interlaken IP solution continues to scale with today’s demand for more bandwidth and higher performance needs.
This application note summarizes the differences between Interlaken IP cores that target the Stratix® 10, Arria® 10, and Stratix® V devices.
Device Family | Stratix® V | Arria® 10 | Stratix® 10 | ||
---|---|---|---|---|---|
IP Core Variant | 50G Interlaken IP core | 100G Interlaken IP core | 50G Interlaken IP core | 100G Interlaken IP core | Interlaken IP core (2nd Generation) 1 |
Protocol Compliant | Interlaken Protocol Specification, Revision 1.2 | Interlaken Protocol Specification, Revision 1.2 | Interlaken Protocol Specification, Revision 1.2 | Interlaken Protocol Specification, Revision 1.2 | Interlaken Protocol Specification, Revision 1.2 |
Supported Lane x Data Rate (per lane) combinations | 8x6.25 Gbps | 24x6.25 Gbps 12x10.3125 Gbps 12x12.5 Gbps |
8x6.25 Gbps | 24x6.25 Gbps 12x10.3125 Gbps 12x12.5 Gbps |
|
Meta-Frame | 128 - 8192 | 128 - 8192 | 128 - 8192 | 128 - 8192 | 64 - 8192 |
Transceiver Reference Clock Frequency | Multiple | Multiple | Multiple | Multiple | Multiple |
Advanced Error Reporting and Handling | Yes | Yes | Yes | Yes | Yes |
M20K ECC Support | No | Yes | No | Yes | Yes |
Diagnostic Features | No | Yes | No | Yes | Yes |
In-band Flow Control Functionality | Yes | Yes | Yes | Yes | Yes |
Transceiver Native PHY ADME | No | No | Yes | Yes | Yes |
Number of Calender Pages | 1, 2, 4, 8, 16 | 1, 2, 4, 8, 16 | 1, 2, 4, 8, 16 | 1, 2, 4, 8, 16 | 1, 2, 4, 8, 16 |
Transfer Mode Selection | Interleaved Packet |
Interleaved Packet |
Interleaved Packet |
Interleaved Packet |
Interleaved Packet |
Data Format | Single segment | Single segment Dual segment |
Single segment | Single segment Dual segment |
Single segment |
Example Design Support | Simulation | Simulation | Simulation Synthesis |
Simulation Synthesis |
Simulation Synthesis |
Resource Utilization - ALMS | 9800 2 , 3 | 17200 2 , 4 | 9900 3 | 17500 4 | 20100 4 |
Resource Utilization -Logic Registers (Primary - P, Secondary - S) 5 | 20700 (P) 1700 (S) |
34200 (P) 2300 (S) |
20600 (P) 1500 (S) |
34100 (P) 1800 (S) |
38000 (P) 9000 (S) |
Resource Utilization - M20K Blocks | 17 2 , 3 | 38 2 , 4 | 17 3 | 38 4 | 44 4 |
1 This IP core is only supported in the Quartus Prime Pro 17.1 Stratix 10 ES Editions. For more details, contact Intel FPGA.
2 For Stratix® V GX devices.
3 IP core variant: 8x6.25
4 IP core variant:12x10.3125
5
Primary registers are the core logic registers; Secondary registers are the implementation, routing and timing closure optimization registers.
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